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RMile
Beginner
1,320 Views

Intel Xeon D1500 10GbE LAN configuration - PHY/PCS registers

Hi,

I need an access to PHY/PCS registers of Xeon D1500 10GbE LAN. For Xeon D1500 family I found only 4 datasheets, in one of them, https://www.intel.com/content/www/us/en/processors/xeon/xeon-d-1500-datasheet-vol-4.html there is some information about LAN configuration, but not enough. I need access to PHY/PCS registers of 10GbE interfaces. There is a link to Appendix B, but there is no register map or other access mode (like MDIO). There is also chapter 8.2.2.11.1 "PHY Indirect Data" and 8.2.2.11.2 "PHY Indirect Control" but there is no explanation what is "16bit address" and no information how to access certain PHY registers. Is there available any other document which describes PHY/PCS registers and access method?

Best regards,

Ryszard

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3 Replies
CarlosAM_INTEL
Moderator
183 Views

Hello, RWM :

Thank you for contacting Intel Embedded Community.

In order to be on the same page, could you please tell us if the affected design has been designed by you or a third-party company? If it is a third-party design, could you please give me all the information related to it? In case that it has been designed by you, could you please confirm us if it has been reviewed by Intel?

Please give us the information that may answer the previous questions.

We really appreciate your collaboration.

Best regards,

Carlos_A.

RMile
Beginner
183 Views

Hello Carlos,

it is our design, it was reviewed by Intel.

Best regards,

Ryszard

CarlosAM_INTEL
Moderator
183 Views

Hello, RWM :

Thanks for your reply.

We suggest you review the information stated in sections 10 and 10.3 of the https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/ethernet-x550-datasheet.pdf Intel(R) Ethernet Controller X550 Datasheet document # 333369.

We hope that this information will be useful.

Best regards,

Carlos_A.

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