Issue: Cannot access boundary scan register (BSR) in boundary scan mode. Broadwell-DE Processor, GG8067402569400 SR2DK

[TYuen3]

Symptoms:

IRCAPTURE register read passes.

IDCODE register read passes.

USERCODE register read passes.

 (from those successes, I conclude that TMS, TCK TDI, TDO, TRST are "working".)

Boundary scan register test, using the PREAMBLE opcode

 Our tools scan in a sentinel pattern, clock the BSR the length of the BSR, count the bits, clock the BSR for the number of bits in the sentinel pattern. The read bits are stored, but not checked for any value until the sentinel pattern is expected. However, if there _is_ a failure, all bits are checked for all ones or all zeros and the tool reports that to the user.

 The first access of the BSR returns all zeros.

 Our tools indicate a failure and only presents that result.

 My next step: I examined the bits in and out during the boundary scan register access. In this test, the BSR is actually tested twice. The first time, the read bits are all ones. However, the second test passes - the sentinel pattern is found, and in the expected bit location.

 I tried various experiments to get the first BSR read to be successful. No change in device behavior.

Question:

Is there something that needs to be done for a successful BSR read?

 An initialization?

 A timing accommodation? (Example, I worked with one device that required the TMS to be delayed 10ms.)

 Is the device sensitive to how the JTAG state machine is transitioned?

 Are two PREAMBLE opcodes required to successfully read the BSR?

Ultimately, for boundary scan testing, it is EXTEST that needs to work, but I cannot get to that phase of testing without first successfully using PREAMBLE and BSR read.

[CarlosAM_INTEL]

Hello, @TYuen3​:

Thank you for contacting Intel Embedded Community.

Could you please clarify that the units related to the cited condition are third-party design or yours?

Could you please give the part number, model, name of the manufacturer, where it is stated the information related to it if it is a third-party project?  

In case it is your design, could you please confirm that it has been reviewed by Intel? Could you please list the sources that you have used to develop it?

By the way, could you please confirm that the reported situation is related to the following forum?

https://forums.intel.com/s/question/0D50P00004SZnQpSAL/ethernet-controller-i350-nhi350am4-slj2zissue-cannot-access-boundary-scan-register-bsr-in-boundary-scan-mode 

We are waiting for your reply.

Best regards,

@Mæcenas_INTEL​.

[TYuen3]

Mæcenas_INTEL (Intel), Is this related to the cited forum question: Basically no. Explanation: Both parts are on the same design. I incorrectly cited the i350. That forum question is invalid and should be terminated or deleted. I should have directed that question to the Broadwell device, which this question. Corelis is a third party providing boundary scan test development services to a customer. I will need to check whether the customer will allow us to provide their name and their design name. Todd Yuen Corelis 13100 Alondra Blvd. Ste. 102 Cerritos, CA 90703 562.926.6727 todd.yuen@corelis.com If you need to send sensitive data to Corelis, please use our secure file transfer system at https://transfer.corelis.com/filedrop/support

[CarlosAM_INTEL]

Hello, @TYuen3​ :

Thanks for your update.

Please use the latest version, which is revision 3 at this moment, of the Intel Xeon Processor D-1500 Product Family Boundary Scan Description Language [BSDL] File document # 549660.

Also, please follow the guidelines and review the information stated in Section 6 Boundary Scan Test JTAG Considerations of the Shark Bay, Denlow, and Broadwell U-Y Platforms Debug Port Design Guide [DPDG] document # 479493.

The CPU JTAG is accessed serially trough five pins (TCK, TMS, TDI, TDO and TRST_N), TMS and TCK are input signals to manipulate or control of TAP controller to Boundary Scan, Identification, Instruction, Data and By-Pass registers during testing.

For more details please refer to the information stated in section 11.1 JTAG Test Mode Description of the Intel(R) Xeon(R) Processor D-1500 Product Family: Datasheet (Vol. 4 of 4) document # 332053.

These documents can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following websites:

https://cdrdv2.intel.com/v1/dl/getContent/549660

https://cdrdv2.intel.com/v1/dl/getContent/479493

https://cdrdv2.intel.com/v1/dl/getContent/332053

The RDC Account Support form is the channel to process your account update request or any inconvenience related to the provided website. It can be found at:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

Best regards,

@Mæcenas_INTEL​.

[leonidK]

Hello,

I meet with the same problem with XEON processor BSDL file.

I'm using BDX_DE_A0_cust_rev3.bsdl file for CPU and

LPT_BDX_cust_rev3.bsdl for PCH.

The PCH device JTAG infrastructure is passed excluding ID Code revision bits.

The CPU device JTAG infrastructure passed all tests exclude BSR length.

I checked it on the Intel Evaluation board. Please look attached files.

The same results I get with 3 Boundary Scan platforms (Corelis, JTAG-Technologies, OnTAP).

Is it possible that it is necessary to launch a pre-sequence before JTAG testing of the device?

- attachments removed by Moderator

[CarlosAM_INTEL]

Hello, @leonidK:

Thank you for contacting Intel Embedded Community.

We want more details about the reported situation. We want to address the following questions:

Could you please provide pictures of the topside markings of the processors related to this situation?

Could you please let us know the place of purchase of these devices?

Could you please list the document numbers of the BSDL files related to this condition and the procedure followed to obtain them?

We are waiting for your answer to these questions.

Best regards,

@CarlosAM_INTEL.

[leonidK]

Hello @CarlosAM_INTEL.

Please look the device image in attached file.

These devices were purchased by Airspan from Intel Europe directly or through our end customer which is Rakuten Japan.

Attachment removed by Moderator

[leonidK]

Also attached used BSDL file.

[CarlosAM_INTEL]

Hello, @leonidK:

Thanks for your updates.

Based on our previous communications, we want to address the following questions:

Could you please inform us of the procedure to obtain the attached BSDL file in your previous message? You should know that the EDC community is a public access tool, which is not the right place to share documents cover under the terms stated in some CNDAs.

Finally, could you please let us know the European company's complete name mentioned in one of your previous replies?

We are waiting for your clarification.

Best regards,

@CarlosAM_INTEL.

[leonidK]

Hello @CarlosAM_INTEL.

Sorry for that. How can I contact you personally?
The BSDL file was obtained by the customer from intel support.
The customer is buying  component from Eastronics

[CarlosAM_INTEL]

Hello, @leonidK:

Thanks for your reply.

Based on your communication,  we want to address the following question:

Could you please let us know the complete name of the first company that you have mentioned in your communication on February, 4th? 

Could you please confirm that this situation is consulted only by you using this thread?

We are waiting for your answer to these questions.

Best regards,

@CarlosAM_INTEL.

[leonidK]

Hello @CarlosAM_INTEL.

The customer company is Airspan Networks.

Regarding the second question: as far as I know - yes, in this thread only.

[CarlosAM_INTEL]

Hello, @leonidK:

Thanks for your reply.

We have sent an email to the address related to your forum account.

Best regards,

@CarlosAM_INTEL.