We are currently working on bring up activity of Xeon d1559 based board, we observed that its successfully powering up from G3 to S5 state, but S3 and S4 state remains in asserted state (Remains LOW)even after the triggering of the pwrbtn# by the FPGA.

[KMANO3]

Please let us know how to proceed further.

[JoseH_Intel]

Hello KMANO3,

Thank you for joining the community

I will transfer your question to the appropriate forum.

For general information please go to https://ark.intel.com/content/www/us/en/ark/products/93352/intel-xeon-processor-d-1559-18m-cache-1-50-ghz.html

Regards

Jose A.

Intel Customer Support Technician

A Contingent Worker at Intel

[CarlosAM_INTEL]

Hello, @KMANO3​:

Thank you for contacting Intel Embedded Community.

Could you please clarify if this situation happens on your design or a third- party design? 

In case that it is a third-party device, could you please inform the name of the manufacturer, its model, the part number, and where its documentation is stated?

On the other hand, could you please let us know how many units of the project related to this circumstance have been manufactured? How many are affected? Could you please give the failure rate? Also, could you please list the sources that you have used to design it and if it has been verified by Intel?

Could you please give pictures of the top side markings of the affected processors? By the way, please provide the part number of the processors associated to this situation.

Finally, could you please explain the procedure that you have used to determine this condition?

We are waiting for your reply.

Best regards,

@Mæcenas_INTEL​.