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E810 NIC - Disable FCS recalculation/insertion

AdriS
Beginner
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Hi,

 

We are using DPDK 20.11(ice driver) with E810 NICs.

We would like to disable Ethernet FCS recalculation/insertion on the E810 NICs. Essentially, when our software passes a packet with an invalid FCS to the NIC to transmit, we don't want the card to recalculate or append the FCS.

For other NICs, the Transmit Data Descriptor register has a bit called something like ICRC or IFCS. However, when I look at the E810 Datasheet, in the Transmit Data Descriptor register, I can't find any bit like that.

See IFCS from the x550 datasheet:

AdriS_0-1682934426376.png


Is this feature supported by the E810 NIC?
Thanks

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4 Replies
B_Y
Employee
886 Views

Hi AdriS,


Thank you for posting in Intel Ethernet Communities.

We need to gather some information so we can provide you recommendations.

- Is this the first time configuration?

- May I know your OS and build version?

- Need your help to Identify Your Wired Intel Ethernet Adapter and Driver Version, please choose the steps according to your OS version:

https://www.intel.com/content/www/us/en/support/articles/000005584/ethernet-products/gigabit-ethernet-controllers-up-to-2-5gbe.html

- May I know if your source of E810 data sheet from here, page 1468: https://www.intel.com/content/www/us/en/content-details/613875/intel-ethernet-controller-e810-datasheet.html?wapkw=E810%20fcs

(Access to may be restricted. Please sign in or register to view.)


Looking forward to your response. Should we not get your reply, we will follow up with you after 2 business days.


Best regards,

BY_Intel

Intel Customer Support


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AdriS
Beginner
870 Views

Thank you very much for your reply. Please see the requested information below:

OS: Ubuntu 20.04.3
Ethernet Adapter: Intel(R) Ethernet Network Adapter E810-XXVDA4
Driver: ICE driver from DPDK 20.01 https://doc.dpdk.org/guides/nics/ice.html
Source of datasheet: the  one you specified above (https://www.intel.com/content/www/us/en/content-details/613875/intel-ethernet-controller-e810-datasheet.html?wapkw=E810%20fcs)

I am not sure about your question "Is this the first time configuration?" . What do you mean by this?

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B_Y
Employee
825 Views

Hi AdriS,


Thank you for your patience. 

May I know if following information helps in your inquiry:

11.8.3.5 Send Operation


The process of posting WRs to UDA SQ and flow is similar to one described for RDMA SQs in Section 11.4.1.5.2.


UDA QP enables the application to transmit individual Ethernet frames per posted SQ WQE. Each transmit WQE must refer to a single Ethernet frame. Software is responsible to limit the frame size to the configured MSS. If frame size exceeds MSS, frame would be discarded and error reported in CQE.


Software is allowed to post Ethernet frames shorter than a minimum Ethernet frame length. Hardware pads Ethernet frames to the minimal Ethernet frame length.


Hardware is responsible for Ethernet FCS and IP checksum generation. Software might request hardware to generate TCP/UDP checksum for non-fragmented datagrams.


In default operation mode, Ethernet and IP headers are generated by hardware using information provided in the address handle. Software can provide additional ULP header (e.g. UDP) either as a part of the application buffer referred by SQ WQE fragments or using a private header ring buffer (if enabled for the QP). If the size of the extended header exceeds the size of the private header ring buffer entry, the packet is discarded and the error is reported in CQE.


Privileged consumers are allowed to post Ethernet frames with all headers. To enable privileged SQ operation mode, the Privileged Header Generation bit should be set at QP creation (see Section 11.8.4).


Software can selectively request completion of WQEs by setting the Signaled bit. Completions with errors are returned regardless of the Signaled bit setting. UDA WQE is completed as soon as hardware finished processing WQE and validated lengths and fragments. Completion of UDA SQ WQE does not indicate that respective Ethernet frames are transmitted or received by the destination. 


May I suggest you to consider reaching out Intel Development Zone since this inquiry more on deployment and development:  

Intel RDC/Intel DevZone account:

How to Apply for an Intel® Resource and Documentation Center (RDC) and/or Intel® Developer Zone (Intel® DevZone) Account:

https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html


Best regards,

BY_Intel

Intel Customer Support


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B_Y
Employee
774 Views

Hi AdriS,


Please be informed that we will now close this request since we haven't received any response from our previous follow ups. Just feel free to post a new question if you may have any other inquiry in the future as this thread will no longer be monitored.


Kindly reach out to Intel Premier Support (IPS) to get support on DPDK.

Steps on How to Register and have Access to Intel® Premier Support:

https://www.intel.com/content/www/us/en/support/articles/000057045/ethernet-products.html


Thank you.


Best regards,

BY_Intel

Intel Customer Support 



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