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I210 AVB Timers

GSing13
Novice
1,550 Views

Hello All,

I am not sure if this is the correct forum to post my question and I would be thankful if someone can point me to the correct one if the question is not relevant.

The question I want to ask is related to the Intel i210-AT chip which I am using for my Industrial solution. I am writing a new Linux driver for the External NIC, which has the i210 chip, for handling packets in a time critical network.

I am using the Time SYNC (section 7.8 in the Intel® Ethernet Controller I210 Datasheet) registers i.e. SYSTIM, TRGTTIML/H0 and TRGTTIML/H1 to create timers using the method explained in "7.8.3.3.1 SYSTIM Synchronized Level Change Generation on SDP Pins"

The timers created are used by the Linux drivers to synchronize the packet transmission in the SR mode (i.e. using launchTime).

I have completed the implementation and the setup works fine if the timers are created in a non-periodic sequence. The problem arises if I try to reset the values or increment the timeout for the timers periodically where the period is lesser than the timeout values.

I am not sure if I have presented my problem correctly here. I would be happy to share other details to clarify the implementation details.

Regards,

Gaurav

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2 Replies
SYeo3
Valued Contributor I
239 Views

Hi Gaurav,

Thank you for contacting Intel. I'll check on this.

Sincerely,

Sandy

GSing13
Novice
239 Views

Hi Sandy,

Do you have any updates for me on the above query?

Regards,

Gaurav

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