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I have an SOPC builder system with the PCI Express (in x4 mode) module instantiated in it. I've attached pins similarly to how the ddr pcie reference design does it (the ddr pcie reference uses the megafunction, but that shouldn't make a difference).
When synthesizing, I'm getting 10 000+ warnings from within the pcie module for reduced registers. I would expect some warnings, but 10 000? Is anyone familiar enough with Altera's PCIe module to know how many warnings are typical when using the SOPC builder version, and where I might start looking for the source of the problem? The reset_n signal is tied to a button input (using the PCIe dev board), and I've tried forcing it to 0 or 1 and the same warnings occur so it's not a reset issue. I've attached a file containing a list of the warnings (warning: it's 5 MB uncompressed). Thanks, BaverLink Copied
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The design sample has approximately the same number of warnings, so I'm guessing it's fine.
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I'm using PCI Express x4 in the SOPC builder flow, and usually reckon on at least 18,000
warnings. Altera say that this is "normal behaviour". I think it is unhelpful in the extreme, because I've had a couple of instances where one really important warning has appeared in the middle of the 18,000 I'm supposed to ignore, and it has obviously taken me ages to realise.
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