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hi
i have a problem that the viterbi ip core is configured as streaming component, and i want to interface it with nios processor, so to do so i must use on chio fifo in the sopc builder to connect them, but the problem is, when i use fifo to convert form Avalon MM to Avalon ST the data width must be 32, but the viterbi data input is 8 bits only, and it's output is only 1 bit !!!! howa can i connect those 2 components, i hope that any one has tried this before can answer men :) thanks :)Link Copied
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