3G-SDI IO standard and pin locking

[Altera_Forum]

Hi, 

 I am trying to do pinlocking for 3G-SDI(tripple rate), what are the standards should i set for refrence clock and differential serial data? when i try to pin lock the differential refrence clock fitter gives an error   "Error: Differential I/O input pin Sdi2HDRefClk is assigned to a non differential location G23. However, it must be assigned to a differential input location"

[Altera_Forum]

how do i stop fitter to generate complementry pins for differential signal?

[Altera_Forum]

I am using quartus 9.0 and Arria II device. why is it so that altera releases tools without doing proper debugging......:mad: it's really disgusting to see that i am stuck because tools behave unusally for Arria II device :mad:

[Altera_Forum]

1 - Let the Pin Planner assign complementary pins for differential interfaces. 

2 - You will have problems if you assign transceiver pins (including reference clocks) but they are not connected to anything in your design. For example, the error you mentioned above could be due to the fact that you declared the pin in your design, you've given it a pin assignment, but it's not used for anything. 3 - The differential serial outputs use the 1.5V PCML standard. 4 - The differential serial inputs can use CML, LVPECL, or LVDS (see table 1-4 in the handbook)  http://www.altera.com/literature/hb/arria-ii-gx/aiigx_5v2.pdf 5 - Table 2-1 shows the supported standards for the reference clocks (same as receivers).  Jake

[Altera_Forum]

Thanks Jake, 

 I will try the sugessions you mentioned.  but why is it so that fitter creates differential pair automatically? below is the warnings message.  Warning: Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.   Warning: Pin "Lvds1RefClk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Lvds1RefClk(n)"   Warning: Pin "Lvds2RefClk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Lvds2RefClk(n)"   Warning: Pin "Lvds1Tx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Lvds1Tx(n)"   Warning: Pin "Lvds1Rx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Lvds1Rx(n)"   Warning: Pin "Lvds2Tx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Lvds2Tx(n)"   Warning: Pin "Lvds2Rx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Lvds2Rx(n)"   Warning: Pin "Sdi2HDRefClk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Sdi2HDRefClk(n)"   Warning: Pin "Sdi1Rx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Sdi1Rx(n)"   Warning: Pin "Sdi1Tx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Sdi1Tx(n)"   Warning: Pin "Sdi1HDRefClk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "Sdi1HDRefClk(n)"   in my previous design i have assigned differential signals but i was not getting these warning messages the only difference between previous design and new design is i was using cyclone III for previous design and Arria II for new design.  One more thing as the tool creates signalname(n) complementry signals how do i define it in entity as () are not allowed in port name.   Thanks, Bhupesh