hi all,I am trying to build a 64bit PCI target using altera IP core, and some error heppens during the mem_rd. What I have done is: 1. generate the IP core using megacore function. 2. generate verilog simulation files. 3. simulate the IP core: using a master to read and write the PCI target I have just generated. 4. cfg_rd & cfg_wr success! 5. mem_rd_64 & mem_wr_64 a qword (64 bit) success! 6. when I tried to form a sequence read using mem_rd_64 task in mstr_pkg.v generated by Quartus, a error happened. The output of AD is x! The picture attached shows single mem_rd waveform. I have checked the waveform, and found out that 4 clk periods after sending addr and command, ad is X, which is just at the cusor's position on the picture attached. But the data period, 0x1234567812345678 on ad is right. while multiple mem_rd, cause the x happened that said above, all the ad read out is x. I am really puzzled about this. The waveform is not the same as it is shown in ug_pci.pdf (altera pci user guide). beside what said above, I have noticed that, on page 3-57 of the user guide, when the 7th clk, ad read out only last one clk period, but in my simulation it lasted 2 clk. I have also do another experiment: generate an 32 bit PCI target, and do the same thing, mem_rd, and I find out all the data is correct. There is no x at the 4th clk period after sending addr and command. I have no idea that if I have made any mistake during the 64 bit PCI target mem_rd. Anyone who knows, would you pls help me! Thx a lot!