About PCI IP core pci_mt32

[Altera_Forum]

I'm evaluating the performance of pci_mt32 core now. 

FPGA act on a master engine, and the PC act as a target. FPGA launch a DMA operation to transfer data into PC.   One problem I am puzzled with is that there is Abnormal Master Transaction Termination occured in the transferring, like disconnect with word, or disconnect without word.    PC can't get the right data if this type error occured in one page memory which is allocated by PC. New page data can be transferred correctly in this circumstance. So I wonder that, how did the fpga re-sent the data to the pc, when this type termination occured?    Any help will be great appreciated.  Thanks

[Altera_Forum]

In order to re-sent data, the FPGA PCI master logic needs to retry the transaction.

[Altera_Forum]

Thanks for your help. 

 Could you elaborate on how to handle the retry command in the master part?When the master detect a Disconnect with data or Disconnect without data in the lm_tsr register, a new transaction will be launched. But the data can not be written into continuous page memory in the computer. It can be written into a new page. I wonder, is there some particular action should be done in the retry data? How to launch the retry command?   Thanks

[Altera_Forum]

I believe the following Design Example found in Altera website should answer your question:  

 http://www/support/examples/verilog/ver-pci-master-memory.html