A bug of LUT component?

[Altera_Forum]

Platform: xp + dsp builder 9.1 sp2 + matlab R2010a 

 The LUT component works well in simulink. When I generate VHDL files and use them in Quartus, its instance outputs only the first value, but never changes when the address input changes.   I check the VHDL file, and find that a SCLR input linked to OPEN. But there is no options related to SCLR in simulink. I manually link SCLR with the same wire linked to ACLR. Then the LUT works.   Is this a bug, or my improper usage of this component?   My problem is that I have to modify code for every instance of LUT, every time I update MDL and autogenerated VHDL files.

[Altera_Forum]

i've seen this or something similar before. i'm fairly certain its fixed in newer versions 

 try using the ROM block instead of the LUT. i don't think it had that problem  i think the problem has to do with the output register of the LUT. try disabling it and using an external delay if the ROM doesn't work  for future reference i think a couple of other blocks had problems with the output register so if your hardware doesn't match Simulink either update to recent software or take a look at post-fit netlists to see if you can see the register disappearing