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Altera_Forum
Honored Contributor I
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AFI Interface Timings for UniPHY

Hello! 

I am trying to use a custom controller to control the UniPHY interface in order to read and write to a DDR2 memory (to be synthesized on a DE3 board). The only timing information I've come across in y searches has been the one included in the External Memory Interface Handbook (EMI) volume 3 section 12, and these diagrams only show single reads and writes onto the AFI but not how to execute consecutive commands. Is it possible to pipeline/interleave the commands in such a way that you start the execution of a new write on the AFI interface while you put out the data of the previous one. According to my understanding, the limiting part is that the dqs_burst signal has to be asserted one clock cycle (memory clock) before the data is put on the bus, and that it has to be zero in the preceeding clock cycle. Is this correct? Doesn't this restriction reduce the memory bandwith considerably, since it is not possible to do seamless writes to the memory? 

 

Best Regards 

Andreas Öhlin
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