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Using DDR Ctrlr and PCIe Mgfnctn on PCI Express Development Kit Stratix II GX Edition

Altera_Forum
Honored Contributor II
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Hi, 

 

We are currently elaborating on PCI Express-to-DDR2 SDRAM Reference Design. The main idea is to use similar architecture - i.e. having our own custom design capable of working with on-board SDRAM memory and streaming data to PC through PCIe. 

 

The provided reference design is capable of performing benchmarking only, i.e. streaming data from and back to PC using provided GUI application. The corresponding reference documentation is inadequate in terms of how the desired design can be implemented. 

 

At the moment we cannot place a data from FPGA into desired memory address in the on-board SDRAM. 

 

Has anyone tried to work in this direction with PCIe DevKit Stratix II GX? Do you have any positive results? 

 

Any comments/suggestions/project files will be most appreciated. 

 

Thanks, 

Maxim.
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Altera_Forum
Honored Contributor II
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Hello, 

Maxim wrote 

 

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The corresponding reference documentation is inadequate in terms of how the desired design can be implemented. 

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I understand the complaints in so far, as the reference design doc (AN431) doesn't explicitely tell how to extent the provided PCIe-to-DDR2 design, e. g. how to share DDR2 instance with another module within your design. User surely would enjoy an instructive example of this kind, but I think, some work must be done by the developer himself. 

 

The basic point is to understand the interfaces available with PCIe and DDR2 controller core. They are well documented in AN431 and in the respective core user guides to my opinion, but probably require some effort to get complete command on it. 

 

I participated in an Arria GX design, one step in testing the hardware was porting the PCIe-to-DDR2 reference design. With Arria GX, a different DDR2 controller is used, but also the native interface in connecting PCIe to RAM. I was mainly engaged with hardware aspects, but I know, that the native interface is almost similar to Avalon and utilizes handshake signals. With their help, it should be possible to insert a multiplexer in the data path to connect your design part. 

 

Regards, 

Frank
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Altera_Forum
Honored Contributor II
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I'm encountering a very similar problem while modifying the SDRAM DDR2 reference design. 

 

The documentation provided by Altera may be adequate for people familiar with the inner details of PCIe but being a PCIe newbie I'm finding it not very comprehensive. I'm more than willing to put in the effort but the gaps in the design walk-throughs don't help...besides replies from Altera support that the "reference design is not meant to be modified" doesn't really help! There is also no information provided on how the SIIGXPCIE.exe functions. 

 

Having modified the reference design, I can write data to the SDRAM but when I read the data using the provided SIIGXPCIe.exe than the data is sometimes not in the order in which I write or doesn't appear to be at the address we specify. This gives the impression that the way we are handling addressing is incorrect. The modifications were made to get a better understanding of the reference design, and we simply replaced the data received from the Rx_Pcie with data from a counter. The burst length size was then hardcoded along with the address at which the data was intended to be written. 

 

Would anyone have any idea on how we can control addressing such that we can write data to a specific address location? Also, any insight on what could be used from the PC-end to create an equivalent to the provided 'SIIGXPCIE.exe' would be most helpful. 

 

Thanks in advance  

Hitul
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Altera_Forum
Honored Contributor II
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I'm encountering a very similar problem while modifying the SDRAM DDR2 reference design. 

Having modified the reference design ............ 

Hitul 

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Hello, schadenfreud! 

How did You manage to modify AN431 ref. design? 

Did any any new information appear in the last 5 years ( since the last post in this thread ) on how to modify AN431 ref. design?
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