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ALT PLL error

Altera_Forum
Honored Contributor II
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Hi ALL, 

 

I have been trying to simulate a PLL in my design, but for some weird reason i get this error again and again : 

 

** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ps Iteration: 0 Instance: /hdlc_test_tb/uut/HDLC_Testing_entity/TxBuff# ** Note: Cyclone IV E PLL was reset# Time: 0 ps Iteration: 4 Instance: /hdlc_test_tb/uut/CLKPLL_MAPING/altpll_component/CYCLONEIII_ALTPLL/M5# ** Note: Cyclone IV E PLL locked to incoming clock# Time: 70 ns Iteration: 3 Instance: /hdlc_test_tb/uut/CLKPLL_MAPING/altpll_component/CYCLONEIII_ALTPLL/M5# ** Error: (vsim-3601) Iteration limit reached at time 710 ns. 

 

 

My clock input is 50Mhz , and i am trying to get c0 => 25Mhz and c1=> 100Mhz , any clues why my simulation get stuck at 710ns ??? 

 

Thanks for reading my post . 

 

Regards ,
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