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Altera_Forum
Honored Contributor I
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Verification of Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA

Hi, teachers. 

 

I want to ask some questions about the " Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA". 

 

1, TX Slave Interface. 

quotes from avalon-mm 256-bit hard ip for pci express user guide (http://www.alterawiki.com/uploads/b/b1/avmm_256_dma_gen3x8.pdf). 

 

page 4. 

the tx slave module propagates 32-bit avalon-mm reads and writesupstream. avalon-mm masters can use this slave port to access pci expressmemory space. the dma controller uses this path to update the dma statusupstream, including msi requests. 

 

page 21. 

the tx slave module translates avalon-mm master read and write requests to pciexpress tlps for the root port. the tx slave control module supports a singleoutstanding non-bursting request. 

 

According to the quotes, we can write data to TX Slave, then the PCI Express IP converts the data to serial data, then send the serial data to host.  

Is my understanding right? 

 

2, Testbench created by Qsys. 

I use Qsys to create the testbench for the "Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA". 

 

I think in the testbench created by Qsys, the serial data is converted to parallel data. Can you tell me which module in testbench implements deserializer function? 

 

If my understanding in Question 1 is right, I think I can find the same data I wrote to the TX Slave Interface. 

 

Thanks in advance, 

zhang
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