FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6228 Discussions

DDR3 memory with Uniphy is SLOW

Honored Contributor II

I don't understand this controller. I have 4 things trying to access the DDR3 memory. I've tried it several different ways, and I seem to have trouble getting it go fast enough. 


So to describe my system: 

I have a Cyclone V with 1GB DDR3 memory @ 32 bits wide. I've been running it at 400MHz without data corruption, but have recently slowed it down to 350MHz because the FPGA couldn't quite keep up. At 350MHz, I calculate a total (albeit unachieveable) bandwidth of 22.4 Gbps. 

Connected to it I have a VIP de-interlacer in HQ mode, a VIP frame buffer the ARM processor and some code of mine. I was struggling because occasionally the de-interlacer or frame buffer would stall, and then when I added my module on I found I couldn't read the data fast enough. I put the internal scope (Signal-Tap II) on my signals and noticed that data was coming in VERY slowly, even through a burst request. About one data word every 6 DDR clocks. Doesn't sound like a burst of data to me! So I wondered if my cycle was somehow being formed incorrectly, so added the Frame Buffer read signals to my internal scope. And that gets data at the same rate. The internal scope picture is attached, where the bottom 6 signals are from the Video Frame Buffer, and the upper 7 are from my code. The clock used to capture the data is actually the video clock, not the DDR half clock, but my "read_count" signal decrements by one for each "out_fifo_writereq" (which is a one cycle delayed readdatavalid signal). 


So that I can get the avalon bus on the DDR memory connected to both Qsys and to my module outside Qsys, I use a Avalon-MM Pipeline Bridge to export the interface for me. The VFB also connects through a Pipeline Bridge (I copied this from a reference design example). The bridges are set to 32 or 512 words max burst size, and "Line wrap bursts" is off. 


I have tried the DDR memory as a soft-controller, or as a MPFE Hard Memory controller, with very similar results. 


I know that DDR memory has an overhead, but it's also designed to do burst transfers. So why is my burst data coming in so slowly? I must be getting something like 3.5 Gbps bandwidth. 


Very frustrated. 


0 Kudos
0 Replies