04-13-2016 10:12 AM
Hello All.I am try make master for write my data to on_chip memory. I am create component, make qsys design. And now have to many i am think simple questions about next step. Guys, please help me understand what assign signals in top level. And exactly i am make all right or no. In generated top-level i am pins for MM master for write data, possible not used pins for write to master or no? And in all cases on-chip memory in my design not initialise if i am run - on-chip memory editor. I am read all what possible and dont understand this. new_component - its top level generated in qsys mem.vhd - similar generated in qsys. Thank you for help and you are time.
04-13-2016 12:55 PM
Hi, kumanika.You can create an on chip memory using MegaWizard or IP catalog, then you can access the memory using the common way. If you have to use the Qsys to create an on chip memory, you need not to create your own "avwrite_0" component, just generate the RTL, then access the RTL generated by Qsys using Avalon-MM Write/Read, because the interface is Avalon-MM interface. You can read "Avalon Interface Specifications" to know how to use Avalon-MM interface. Best regards, zhang
04-13-2016 01:39 PM
Hello zhangfeng!I am read Avalon spec, read habdbook etc. From avalon spec - to many signals very intresting and i am dont know what correctly declare this. I am simply not understand this is step. Normaly in all cases same what for pci, for avalon - need master, i am create master for use this to read /write functions, only after generate rtl (in my attach ) dont know what is it make. - its general question. Thank you for answer.