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Altera_Forum
Honored Contributor I
1,706 Views

ALT2GXB Help................

Hi, 

 

I am using the ALT2GXB with the Stratix II GX ep2sgx90ff1508c3 board... 

I configured the GXB using the Mega core from the quartus...  

When I run the GXB on the hardware the recieved data is different from the transmitted data.. 

Actually I gave the output of the counter(16bit counter running at 312.5MHz) as the transmitter input to the GXB.... 

I used the Locations as G1,G4 in the FPGA as the RXDATA & TXDATA (serial lines) connected to the HSMA TX_P3 & HSMA_RX_P3 pair.... 

 

I have attached the BDF file that I used as my design.Also the CSV file obtained while running the Signal tap II analyser.... 

 

DO i have missed anything while configuring the ALT2GXB..... 

 

Thanks 

Santosh
0 Kudos
23 Replies
Altera_Forum
Honored Contributor I
47 Views

Hi  

I am doing a project on the serial communication using the transceivers present in the Stratix II GX ep2sgx90ff1508c3 

For this i am using the HSMC connector slot available on the board for the loopback operation. 

SO now I have 6 TX-RX channels on HSMA & 4 TX-RX channels on HSMB connections.. 

 

If I insert the HSMC cards(connectors) that is attached here in the HSMC slot the loopback operation should work properly right??? 

Or if any other hardware need to be connected like cables to HSMC connectors as told in the High Speed Mezzanine Card (HSMC) 

Specification link:www.altera.com/literature/ds/hsmc_spec.pdf ??? 

Apart from assigning the TXDATA & RXDATA pin locations that are available on the HSMC connectors any other signals should be  

assigned while doing pin assignment. I only assigned the TXDATA & RXDATA pin locations thats it.... 

Should I assigned the signals like HSMA_CLK_IN0,JTAG_TDO,JTAG_TMS,HSMA_D0-D3,HSMA_JTAG_TDO,JTAG_TCK,HSMA_SDA.... 

 

I am new to the HSMC connectors please any one who knows about it ........ 

please reply.......
Altera_Forum
Honored Contributor I
47 Views

you only need TXDATA and RXDATA assignments for the GXBs

Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

 

When I run the GXB on the hardware the recieved data is different from the transmitted data.. 

Actually I gave the output of the counter(16bit counter running at 312.5MHz) as the transmitter input to the GXB.... 

 

--- Quote End ---  

I didn't look at your design files, but I'll tell you what you should have. 

 

The TX-to-RX path is serial, so whatever you send in parallel at the transmitter can be misaligned by any number of bits when received at the receiver. The receivers have word-alignment and bit-slipping controls. You need to first use those to align the receiver to your transmitted 8-bit/16-bit/32-bit data, and only then will your transmit data and receive data match. For example, you could send the static pattern ABCDh, and bit-slip at the receiver until you start receiving ABCDh, and then you would switch the transmitter to your counter. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

Dear Sir, 

 

Thank you very much for the reply.......... 

 

I want to know how to make the receiver being aligned to the txdata for the first time... 

 

can you suggest some documents which can guide more about this alignment.......... 

 

 

 

--- Quote Start ---  

I didn't look at your design files, but I'll tell you what you should have. 

 

The TX-to-RX path is serial, so whatever you send in parallel at the transmitter can be misaligned by any number of bits when received at the receiver. The receivers have word-alignment and bit-slipping controls. You need to first use those to align the receiver to your transmitted 8-bit/16-bit/32-bit data, and only then will your transmit data and receive data match. For example, you could send the static pattern ABCDh, and bit-slip at the receiver until you start receiving ABCDh, and then you would switch the transmitter to your counter. 

 

Cheers, 

Dave 

--- Quote End ---  

Altera_Forum
Honored Contributor I
47 Views

Create a Modelsim simulation with the transceiver and test the different control signals in that. 

 

Then in hardware use SignalTap II to compare the simulation to the hardware. SignalTap will not be able to probe the high-speed SERDES lanes and internal GXB signals, but you will be able to see how the received parallel output pattern is bit-shifted relative to the transmit pattern. 

 

Start with some simple patterns, eg. 5555h will be received as either 5555h or AAAAh, and if you assert the bit-slip control, you can change (bit-slip) the pattern. 

 

There are some transceiver debug application notes and online webinars. Look on the Altera web site. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

I will try the Simulation of the transceiver,,,,,,,,,,,, 

 

A small doubt...Do the transceiver tool kit available in the quartus II is applicable to the Stratix II GX devices also ???.... 

Can we characterize the transceiver features when we are using the transceivers along with the HSMC loopback connections.........  

 

 

--- Quote Start ---  

Create a Modelsim simulation with the transceiver and test the different control signals in that. 

 

Then in hardware use SignalTap II to compare the simulation to the hardware. SignalTap will not be able to probe the high-speed SERDES lanes and internal GXB signals, but you will be able to see how the received parallel output pattern is bit-shifted relative to the transmit pattern. 

 

Start with some simple patterns, eg. 5555h will be received as either 5555h or AAAAh, and if you assert the bit-slip control, you can change (bit-slip) the pattern. 

 

There are some transceiver debug application notes and online webinars. Look on the Altera web site. 

 

Cheers, 

Dave 

--- Quote End ---  

Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

Do the transceiver tool kit available in the quartus II is applicable to the Stratix II GX devices also ??? 

 

--- Quote End ---  

I am not using the Stratix II GX, so I do not know. 

 

However, for the Stratix IV devices, it was not particularly difficult to implement the same functionality directly; using Avalon interfaces in the hardware and System Console Tcl scripts for access. 

 

 

--- Quote Start ---  

 

Can we characterize the transceiver features when we are using the transceivers along with the HSMC loopback connections......... 

--- Quote End ---  

Sure. Samtec also sell HSMC-to-SMA adapters for about $500 each. They're useful for interfacing to different boards, and they allow you to test links with DC blocks etc. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

I guess if we use only HSMC connectors, we can't characterize transceiver using the transceiver tool kit of quartus.... 

right......... 

 

 

--- Quote Start ---  

I am not using the Stratix II GX, so I do not know. 

 

However, for the Stratix IV devices, it was not particularly difficult to implement the same functionality directly; using Avalon interfaces in the hardware and System Console Tcl scripts for access. 

 

Sure. Samtec also sell HSMC-to-SMA adapters for about $500 each. They're useful for interfacing to different boards, and they allow you to test links with DC blocks etc. 

 

Cheers, 

Dave 

--- Quote End ---  

Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

I guess if we use only HSMC connectors, we can't characterize transceiver using the transceiver tool kit of quartus.... 

right......... 

--- Quote End ---  

Why do you think that?  

 

What do you want to characterize?  

 

If you want to probe signals with an oscilloscope, you can do that on the BGA vias. But that does not really tell you much at high frequencies, unless you have a fancy scope with equivalent equalizer settings. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

Dear Sir.......... 

 

If possible I want to check the actual rate of the transceiver... 

Features like eye diagram...bit error rate.... 

How we can do............
Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

 

If possible I want to check the actual rate of the transceiver... 

Features like eye diagram...bit error rate.... 

How we can do............ 

--- Quote End ---  

The rate of your transceiver depends on how you configure it. If you configure it for 5000Mbps, and the transmit and receive PLLs are locked, and the link transfers valid data, then, assuming your references are precise, the 'actual rate' is 5000Mbps. 

 

The eye diagram can be analyzed using the eyeQ feature of the transceiver; this feature is available with the Stratix IV devices, I'm not sure about the Stratix II GX. 

 

The bit-error rate can be tested using a pseudo-random binary sequence (PRBS). A PRBS is a sequence of bits with properties that are a good stress-test of a serial link. When a PRBS pattern is received it can be used as the seed for a receiver-side PRBS generator. Once the receive side PRBS is initialized, the transmitter and receiver PRBS data can be XORed together. If the patterns match, then the result of the XOR is zero, whereas if there are bit-errors, bits will be set. If you count the number of bits set over a long period of time, you create a bit-error-rate tester. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

Thank you Sir....for the nice reply..... 

 

:):)Good news is I am receiving the correct data now what i have transmitted,,,,,,Earlier the TX_CTRLENABLE  

was not asserted,after asserting I am getting correct rxdata,before which the reset sequence for both TX & RX were completed:):) 

 

I am sending 16bits per cycle as input to the parallel data to transceiver....and receiving the correct data......... 

 

 

Right now What I did was I set a counter whose output is connected to the parallel data section of Transmitter... 

But I want to enhance this project using some other IP's..... 

The thing is I want to transfer data using serial communication.... 

I want to have some design which can tranfer data between the PC and the FPGA board,then the Data is tranfered through the FPGA serial link,,,,,, 

Again the received data shall be saved in PC only.....here transfer is within only a single PC .....but it can also be extended to other PC too... 

I have time only to do communication within a PC...... 

I want your suggestions please about how Can I proceed further......
Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

 

Good news is I am receiving the correct data now what i have transmitted,,,,,,Earlier the TX_CTRLENABLE  

was not asserted,after asserting I am getting correct rxdata,before which the reset sequence for both TX & RX were completed 

 

--- Quote End ---  

Great! Now that you have got it working in hardware, go back and get it working in simulation. The simulation will help you 'see' parts of the system that will be difficult to observe using an oscilloscope, or help you compare signals you can capture using SignalTapII. 

 

 

--- Quote Start ---  

 

The thing is I want to transfer data using serial communication.... 

I want to have some design which can tranfer data between the PC and the FPGA board,then the Data is tranfered through the FPGA serial link,,,,,, 

Again the received data shall be saved in PC only.....here transfer is within only a single PC .....but it can also be extended to other PC too... 

I have time only to do communication within a PC...... 

I want your suggestions please about how Can I proceed further...... 

--- Quote End ---  

If you want to transfer data from the PC-to-FPGA via the serial link, then you will have to use a protocol that a PC can use. PCIe and 10GbE are a couple of possible options. For example, I use a laptop ExpressCard (PCIe) to communicate with the PCIe-based Stratix IV GX development kit. See the discussion here: 

 

http://www.alteraforum.com/forum/showthread.php?t=29851 

 

If you want to use the serial links between two FPGAs, then you can choice the protocol yourself. Altera has an IP core called SerialLite II that might be appropriate. I haven't looked at it, but plan on checking it out. Let me know if it works out for you. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

I am thinking of using the PCIe feature ....by plugging the PCIe into the motherboard........... 

Can i get some reference design for this............
Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

I am thinking of using the PCIe feature ....by plugging the PCIe into the motherboard........... 

Can i get some reference design for this............ 

--- Quote End ---  

 

 

There are examples on the Altera web site, there is an example on the Altera Wiki, and I think there is a webinar on the topic too. If there is a PCIe evaluation board for the Stratix II GX device, then it probably has an example design. You'll have to do a little research. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

Hi.... 

 

I am trying to use the PCIe in my design..... 

Please tell me how to detect the PCIe while the system is booting.... 

In the Stratix II GX(EP2GX90FF1508C3) device how to configure the PCIe at the time of the Booting... 

 

Which flash device need to be used.... 

I am able to find the EPM570 & EP2SGX90 devices in the chain.....
Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

 

I am trying to use the PCIe in my design..... 

Please tell me how to detect the PCIe while the system is booting.... 

 

--- Quote End ---  

The FPGA must be configured in PCIe mode in time for the BIOS to configure the PCIe interface memory windows. For the Stratix IV GX development kit, I usually power-on the host machine and put it into its BIOS page. Turning on the host powers on the development kit in an external PCIe motherboard. I then use another machine to configure the development kit with a PCIe design. I then let the host boot; its BIOS configures the PCIe interface. I can then see the PCIe device from Windows or Linux on the host. 

 

 

--- Quote Start ---  

 

In the Stratix II GX(EP2GX90FF1508C3) device how to configure the PCIe at the time of the Booting... 

Which flash device need to be used.... 

I am able to find the EPM570 & EP2SGX90 devices in the chain..... 

--- Quote End ---  

Generally you want to configure as fast as possible, so if you have parallel output flash connected to the FPGA configuration interface, use that. 

 

If you cannot configure the PCIe interface fast enough, then you might be able to trigger your OS to perform a re-enumeration of the PCI bus. This OS feature is used when hot-swapping PCI devices, so you might have to come up with a scheme of generating a fake hot-swap event for your PCIe board. 

 

I haven't looked into the details of this for PCIe boards. I know it is possible for compactPCI boards and Linux, but its not a mainline kernel feature. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
47 Views

One more thing about thing about the PCIe, 

We have bars present in the PCIe...corresponding to the memory size that depends on the configuration we choose.... 

I know that this memory resides in the system.... 

I want to know where exactly this memory is located???  

for example if bar0 and bar1 are 1Mb & 2Gb SIZE where exactly they are located...
Altera_Forum
Honored Contributor I
47 Views

Dear Sir, 

 

I saw in the document Stratix II GX PCI Express Development Board that is present in the following link  

 

www.altera.com/literature/manual/mnl-s (http://www.altera.com/literature/manual/mnl-s)2gx-pci-express-devkit.pdf 

 

in the fpp configuration section(page 24) we have the figure 2–8. which explains the concept for the pcie configuration, in this we have to select config_mode[1:0] as "00" & dipsw+pgm[2:0] for the configuration file page select - 0,1,2..... 

 

in the same pdf under the max ii cpld configuration controller(page 27) it was told to use the pfl mega function ..... 

 

can you please explain me how we can use these in the pcie identification.......