You would have 2 inputs each with a 7-bit deserialization factor. This would give you two 7 bit data buses of which one is the upper 7 bits and one is the lower 7 bits. These are then concatenated together to make the 14bit wide data bus.Assuming you have a frame clock, then you don't use DDR as such, but use a PLL to generate the bit clock from the frame clock at a high enough frequency to clock you data stream. If the data is DDR, you may have to use the ALTLVDS module in external PLL mode and instantiate a PLL instance for your required frequencies.
thanks TCWORLD, can i be really adventurous and add 16 LVDS pairs (from the 8 ADC channels) into a single altlvds_rx receiver block, which in turn is fed be an external pll, or am i speaking plain stupidity. opinions will be much appreciated. thanks.
You should be able to, but you need to check the FPGA datasheet. There are rules about which SERDES blocks can be fed by which PLLs. If your 16 LVDS inputs cannot be fed by the same PLL, then you will have to break the 16 down into smaller blocks.I've use 8 LVDS pairs in a block before. I could have used 16 on the same PLL in one of the Stratix IV's. I don't know about the Cyclone II's .
thanks TCWORLD, cyclone II has so called IOE's but no SERDES block from the looks of it. the altlvds_rx is implemented using LE's within the device, don't know how good or bad this is? if i find anything about pll fan out in cyclone II i shall report back. thanks.
Ah right, in which case you can make the ALTLVDS block as many channels as you have logic elements for. What you will find though is heavy restrictions on the Fmax as deserialization is implemented in logic. Only time(quest) will tell if it will be fast enough for your applicaiton.
hi, zoulzubazz.Could you attach that two pictures again? They are too small to see clearly. --- Quote Start --- http://www.alteraforum.com/forum/attachment.php?attachmentid=10601&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=10602&stc=1 hey guys, attached is the block diagram for a deserialiser unit (deseralization factor 6) constructed using altlvds_rx megafunction. this is for cyclone ii so there is no dedicated hardware for deserialization. input data rate from ADC is 300mbps, it is in DDR format and each frame is 6 bits long making the frame clock (clkin in timing diagram) 50MHz. this frame clock is fed into a pll to generate the bit clock (rxclk) at 150 MHz. I am attaching the block diagram and a snapshot of the timing diagram for a functional simulation where the data is high for a rising edge and falling edge of the bitclock. the concern is the delay between the change in the input data (datain) and the time required to register this change at rx (it takes four clock edges before rx changes). is this normal? is there a way to fix this. thanks. --- Quote End ---
Hi, TCWORLD.I'm confused about how to use frame clk from the A/D converter. Can I not use frame clk? Just connect LVDS channels to ALTLVDS_RX? Thanks in advance.
--- Quote Start --- I'm confused about how to use frame clk from the A/D converter. Can I not use frame clk? Just connect LVDS channels to ALTLVDS_RX? --- Quote End --- You must use frame clock (or bit clock) from A/D converter for clocking ALTLVDS_RX megafunction.
--- Quote Start --- You must use frame clock (or bit clock) from A/D converter for clocking ALTLVDS_RX megafunction. --- Quote End --- Hi andrei. Thank you for taking the time to answer my questions. I'll use bit clock as the the input clock of ALTLVDS_RX's internal PLL, and use frame clock to decide whether to pulse rx_channel_data_align or not. Regards, zhangfeng