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Altera_Forum
Honored Contributor I
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ALTLVDS_Rx

Hi guy, 

 

Now I use the ALTLVDS_Rx component in my design. When the number of channels is 8 and the deserialization factor is 1 , it's clear, reading the lvds bus will get the correct input data. The input data and output data is rx_in[7..0] and rx_out[7..0]. 

 

If the deserialization factor is 4, the output data is rx_out[31..0].I don't known the 8 channels correspond to which bits of rx_out[31..0] respectively. 

 

 

Any advice, thanks.
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Altera_Forum
Honored Contributor I
39 Views

 

--- Quote Start ---  

Hi guy, 

 

Now I use the ALTLVDS_Rx component in my design. When the number of channels is 8 and the deserialization factor is 1 , it's clear, reading the lvds bus will get the correct input data. The input data and output data is rx_in[7..0] and rx_out[7..0]. 

 

If the deserialization factor is 4, the output data is rx_out[31..0].I don't known the 8 channels correspond to which bits of rx_out[31..0] respectively. 

 

 

Any advice, thanks. 

--- Quote End ---  

 

 

Search for 'rx_channel_data_align' in the LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide. In particular, take a look at the following: 

- Page 2-13 (page 15) which describes how you manually align the bits 

- Page 3-8 (page 36) which describes this process in more detail. 

 

I was a bit surprised when first encountering this years ago, having become used to commercial Camera Link parts which lock on and define bits relative to the input clock (not the higher speed bit clock). 

 

Kevin Jennings
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