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Altera_Forum
Honored Contributor I
891 Views

How to change output format in Clocked Video Output

Hi, 

 

I have a question relating to the output stage of my VIP system. I have my video path working sending out 1080p @ 60 from a frame buffer without issues.  

 

My goal is to have the system output 50 and 60Hz user selectable from NIOS.  

 

Even though I try and change the 24 registers (or so) on the fly using NIOS IOWR_32DIRECT(etc..) the system never applies any of the values...I have pulled down the "valid" signal first and tried several things to no avail.. 

 

However, if I go ahead and recompile SOPC using the 50Hz sync values as hardcoded then everything is beautiful and proper at 50Hz..but of course this is not desired as it needs to be on the fly. 

 

I am wondering if this has something to do with control packets that I should inject into the stream prior to CVO? I just don't see any sync information there, only resolution and that doesn't change between 50/60Hz... 

 

Can anyone point to the right direction?
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6 Replies
Altera_Forum
Honored Contributor I
38 Views

I haven't actually done what you are trying to do, but based on the documentation and other VIP experience, I have a couple ideas: 

 

1. Are you clearing the GO bit, waiting for the STATUS bit to be cleared and then setting the GO bit again? (See the Avalon-MM Slave Interfaces section of the VIP document for some more details). 

 

2. The CVO supports multiple banks of output configurations. If you have a 60Hz configuration before the 50 Hz one, you must disable the 60Hz configuration for it to use the later one.
Altera_Forum
Honored Contributor I
38 Views

Thanks Kevin, I tried to play with the GO-bit earlier as well but I didn't try the enabling/disabling. I'll test it.

Altera_Forum
Honored Contributor I
38 Views

I did some more investigations and I am still unable to perform the change.. This was what I did: 

 

1. Set GO-bit to zero 

2. Wait till status = 0 

3. pulled valid (reg address 28 decimal) low 

4. rewrote all 24 registers and set valid back high 

5. set GO-bit to 1 

 

What happened was that picture went away and came back as it was originally.. no change 

 

Then I went to investigate what is actually in the registers and found out that I can't read them... The only readback values come from the first 5 regs (0-4) which include the status/interrupt/used words etc..Is this true? That all video-related registers in CVO all are write-only? 

 

Anyway, since all this didn't solve my original problem I have to try something new..maybe play with control packets? Anyone have any ideas there?
Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

Is this true? That all video-related registers in CVO all are write-only? 

--- Quote End ---  

The VIP manual does state in a footnote to the CVO register table: 

--- Quote Start ---  

(1) The rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only. 

--- Quote End ---  

I also noticed the manual states the following: 

--- Quote Start ---  

When the MegaCore function receives a new control packet on the Avalon-ST Video input, it searches the mode registers for a mode that is valid and has a field width and height that matches the width and height in the control packet. 

--- Quote End ---  

Perhaps the control packet actually has to change to be considered a new control packet? Although, it seems like there should be a way to easily force new mode settings even if the frame size has not changed.
Altera_Forum
Honored Contributor I
38 Views

Another thought: 

 

Have you tried configuring the CVO to include more than one set of mode registers? Perhaps the CVO requires at least two sets of mode registers to properly support multiple run time configurable modes.
Altera_Forum
Honored Contributor I
38 Views

hsj...I am working with Quartus 11.1 with the CVO and am trying to do realtime config between 720x480p and 640x480p. I originally overlooked address 28 which is the 'valid' reg. really important to set that after Nios has configured Mode1. 

 

Also, CVO doesn't care about your clock...how are you changing freq? Do you have a memory mapped PLL? I am going to add that but I currently have the PLL hardcoded in Verilog, not in Qsys system, running at 27Mhz.
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