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Altera_Forum
Honored Contributor I
790 Views

the waitrequest of avalon bus

Hi: 

the output shoud use the register many paper write that,but I find that if the waitrequest output with register will lead to delay a cycle.it is difficult to design the register timing.if use the combinational logic will solve the problem.but I am not sure whether it is reliable. 

thank you!
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5 Replies
Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

Hi: 

the output shoud use the register many paper write that,but I find that if the waitrequest output with register will lead to delay a cycle.it is difficult to design the register timing.if use the combinational logic will solve the problem.but I am not sure whether it is reliable. 

thank you! 

--- Quote End ---  

 

 

Typically, one can design the wait request output to be the output of a flip flop, but it is not a requirement. There is nothing unreliable about using combinatorial logic. 

 

If you're having difficulty with the output being a flop and would like it to be one, then take note that the wait request output is a don't care while the read/write controls are inactive. This implies that wait request can be a 1 during those times. That way, on the clock cycle when read or write changes to a 1, wait request will already be set to 1 to give you the wait cycle that you need. Once you're ready to release wait request you clear it for the next clock cycle. 

 

If you have a more specific question, ask. 

 

Kevin Jennings
Altera_Forum
Honored Contributor I
55 Views

If the waitrequest is output of a flip flop, when use the avalon bus transfer the data to the FIFO,there is a data cann't be stored. For example,when the data2 sampled by the FIFO,there is no space and full pull up,at next cycle the full signal will be sampled and the next cycle waitrequest will be pull up.that means data3 will be losed. 

If the waitrequest output with the combinational logic,there is no problem,when the full pull up,the waitrequest will pull up at the same cycle. but the output delay of waitrequest will be increased, it's bad for synthsis. 

thank you!
Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

If the waitrequest is output of a flip flop, when use the avalon bus transfer the data to the FIFO,there is a data cann't be stored. For example,when the data2 sampled by the FIFO,there is no space and full pull up,at next cycle the full signal will be sampled and the next cycle waitrequest will be pull up.that means data3 will be losed. 

If the waitrequest output with the combinational logic,there is no problem,when the full pull up,the waitrequest will pull up at the same cycle. but the output delay of waitrequest will be increased, it's bad for synthsis. 

thank you! 

--- Quote End ---  

 

 

The situation you described isn't really correct. In the case that you show, wait request should be set to Fifo full. No logic, just connect it. Fifo full will typically be the output of a flip flop, therefore so would wait request. 

 

What you showed is an incorrectly implemented wait request since the component indicated that it accepted the data (write = 1, wait request = 0) when it did not because the Fifo is full. This is logically incorrect and would result in a system failure so comparing it to anything that is logically correct is pointless. 

 

Similarly, a component that has a fifo output interface that needs to be Avalon compliant would simply use the fifo empty for the wait request. Again, simply connect wait request to fifo empty, no logic. 

 

What I believe you were stating in the original post was that it is difficult to generate a wait request signal that is an output from a flip flop. As I stated in my first post in general, and here in the specific cases of fifos, it is typically not too hard to have wait request come out of a flip flop. That doesn't mean that it is always the case, just that usually you can.  

 

If the component has a single interface that has a fifo for reading and writing one would have to either modify the fifo component to produce slightly differerent status outputs in order to create a wait request that is the output of a flip flop or combinatorially mux the full and empty signals based on read (or write) to select the appropriate one. 

 

The short description for an implementation of wait request for any Avalon component is: 

- For an interface that can only be written to, the component should create a 'Ready for Input' signal. Wait request = not(Ready for Input). 

- For an interface that can only be read from, the component should create an 'Output Ready' signal. Wait request = not(Output Ready). 

- For an interface that can be written and read, Wait Request = Ready for Input when Write = 1, else Output Ready is one simple implementation...there are others. 

 

In the particular case of a fifo, one should be able to easily see the following relations are true: 

 

Ready for Input = not(Full) 

Output Ready = not(Empty) 

 

Kevin Jennings
Altera_Forum
Honored Contributor I
55 Views

But in some particular case,the waitrequest is not only controlled by the full,some other factors may lead to the data cann't be received by the slave,in other words even though the FIFO is not full,the waitrequest may need to pull up. 

 

thank you!
Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

But in some particular case,the waitrequest is not only controlled by the full,some other factors may lead to the data cann't be received by the slave,in other words even though the FIFO is not full,the waitrequest may need to pull up. 

 

thank you! 

--- Quote End ---  

 

 

You're the one who presented the case of the fifo, not me. I presented the correct logic to implement wait request as a flip flop using the status output of the fifo. That is the correct solution to that particular problem. If you have some particular problem that you're trying to optimize you should post it. 

 

I don't disagree that there may be other factors that would enter into whether or not wait request can come directly out of a flip flop, I even presented a case where it couldn't at least not without more specific information about the particular application. 

 

Not every case can wait request be generated as the output of a flip flop...but that is not a requirement of Avalon. If you follow the formula I gave in the last post, you'll get it as good as it gets within the given interface selection. 

 

Kevin Jennings
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