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Altera_Forum
Honored Contributor I
1,219 Views

ALTMEMPHY used on STRATRAX-III have ERROR when synthesis!

In my design, I used a DDR SDRAM PHY (ALTMEMPHY) generated by Quartus-II megawizard tool. When in synthesis, occured errors as bellow. I can't resolve this problem. Please give me your advice, thanks a lot. 

 

Error: Output port "O" of PSEUDO_DIFF_OUT primitive "ddr_phy:u_ddr_phy|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|ddr_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_pdiff" must drive only one OBUF primitive on the I port and cannot drive anything else File: D:/fpga/mega_ip/altmemphy/ddr_phy_alt_mem_phy.v Line: 5186 

 

Warning: PLL "ddr_phy:u_ddr_phy|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|ddr_phy_alt_mem_phy_clk_reset:clk|ddr_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_17r3:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected 

 

Error: Input port DATAIN of DDIO_IN primitive "ddr_phy:u_ddr_phy|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|ddr_phy_alt_mem_phy_clk_reset:clk|ddio_mimic" must come from an I/O IBUF or DELAY_CHAIN primitive File: D:/fpga/mega_ip/altmemphy/ddr_phy_alt_mem_phy.v Line: 5099
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4 Replies
Altera_Forum
Honored Contributor I
43 Views

hi, i have met this issue too. 

Do you have fixed it?
Altera_Forum
Honored Contributor I
43 Views

yes, you must make sure your pin assignment is ok before synthesis. you can use the auto-generated pin_assignment.tcl to configure the pin assignment, but do this first, you must read the tcl file and somtimes need modify it according to your project and memory requirement, for example 1.8V or 2.5V, ect. 

 

Good luck!
Altera_Forum
Honored Contributor I
43 Views

thanks , i have fix it~

Altera_Forum
Honored Contributor I
43 Views

Hi , 

 

I am having a project with EP2AGX125EF35C4 as my FPGA and MT41J64M16LA-15E as my SDRAM device. 

In SOPC builder design, I have taken DDR3 SDRAM controller with ALTMEMPHY. In selected memory preset I have choosen MT41J64M16LA-15E. 

 

Now I have changed my FPGA device from EP2AGX125EF35C4 to EP2AGX125EF35I5. DDR3 device is MT41J64M16LA-15EITB. 

 

In short, I have migrated my project from commercial grade to Industrail grade. 

 

I am getting error as Timing requiements not met and DDR Timing requiements not met. 

 

Please tell me, What changes should be done to meet DDR3 Timing requirements if I am migrating my project from use of EP2AGX125EF35C4 as FPGA to EP2AGX125EF35I5 as FPGA.
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