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SMS
Beginner
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ALTPLL Error: Clock Input port of PLL must be driven by non-inverted input pin or another PLL.

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Device: Max10 (10M16SAE144I7G)

I am trying to use the ALTPLL IP core in my design for frequency synthesis. The clock input of the ALTPLL is directly fed by external oscillator via one of the dedicated clock input pin (have tried multiple pins incl. pin # 26, 27, 88, 89), but each time it gives the following error.

 

Error (15065): Clock input port inclk[0] of PLL "PLL_block:pll|altpll:altpll_component|PLL_block_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

 

Info (15024): Input port INCLK[0] of node "PLL_block:pll|altpll:altpll_component|PLL_block_altpll:auto_generated|pll1" is driven by clk_100MHz which is COMBOUT output port of Combinational cell type node clk_100MHz

 

I have also tried to add a clock control block between the external oscillator input and PLL but the same error repeats. Can someone please help me figure this out?

 

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1 Solution
398 Views

Hello, Sorry for delay , I caught into another stuff,

Today morning i get chance to look at your design files , Here is changes i did which made it work

i) Add wire clk_200MHz (which is missing in your top module )

ii) removed th /*synthesis keep */ in clk_int. After these changes it is working for me.

 

One more thing i noticed is , LVDS IP is opted for internal clock and input of the clock is feed from PLL. iam not sure why ..but i can say it is going to take more PLL resources

 

Let me know if you have any question /concern ?

 

Thank you ,

 

Regards,

Sree

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9 Replies
398 Views
Hello , Can you let me know in which pin exactly clock is connected ? from the error it is very clear that clock is connected to the inverted pin which is name_N. If the clock input to the FPGA is single ended it must need to connect to the pin_P (non-inverted ). Also if you still facing the issue , can you also try below constraint https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti... Thank you , Regards, Sree
SMS
Beginner
398 Views

I first got this error even before I had done any pin assignment. After that I tried assigning CLK2n Pin # 89 (yes that is an inverted pin), CLK2p Pin # 88, CLK0n Pin # 26, CLK0p Pin # 27 to the single ended clock input, but the error persisted.

 

Thanks for sharing the KDB solution, I will try it and report any progress here.

 

398 Views
Sure , if you attach the .qar file i can take a look and try to solve the same Thank you , Regards, Sree
SMS
Beginner
398 Views

Project archive attached. Thanks

SMS
Beginner
398 Views

I have tried the solution suggested in KDB article shared above. I couldn't find the command assigning blackbox to any level of hierarchy, still I added the suggested command, but the error persists. I have also tried adding multiple PLL clock inputs, that too does not effect this error.

SMS
Beginner
398 Views

Can someone please help me resolve this issue. Thanks

399 Views

Hello, Sorry for delay , I caught into another stuff,

Today morning i get chance to look at your design files , Here is changes i did which made it work

i) Add wire clk_200MHz (which is missing in your top module )

ii) removed th /*synthesis keep */ in clk_int. After these changes it is working for me.

 

One more thing i noticed is , LVDS IP is opted for internal clock and input of the clock is feed from PLL. iam not sure why ..but i can say it is going to take more PLL resources

 

Let me know if you have any question /concern ?

 

Thank you ,

 

Regards,

Sree

View solution in original post

SMS
Beginner
398 Views

Thanks Sree that helped. I don't know why but it looks like optimization can't be skipped for ALTPLL IP core.

 

And yes the LVDS IP core is also using PLL. In fact if LVDS IP core is configured to use internal clock it uses all available PLL resources instead of using only one output of the PLL. Would like to know why this happens.

398 Views

Hello ,

Sorry ; I just noticed you have questions, Really apologize

Even when you use the internal PLL setting in the LVDS IP , It will still use the same PLL what is available in the bank.

I am not sure how i answered your questions .

 

Thank you ,

 

Regards,

Sree

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