ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

[Heyang]

Hi friends,

I’m using the ALTPLL dynamic phase reconfiguration feature to emulate an all-digital PLL without relying on an analog VCO.

Setup: the PLL takes a 50 MHz input and generates c0, c1, and c2, all at 50 MHz. I based my state machine on Intel’s example (AN-454, https://cdrdv2-public.intel.com/653845/an454.pdf, and have attached my code. For testing, the original 50 MHz reference is routed to a GPIO pin, and the phase-shifted clock is routed to SMA_CLKOUT_p. To switch which output is phase-shifted, you can modify lines 161 and 203 in the PLL_phase_shifter.v.

Observed behavior:

• With the code unchanged except for PHASECOUNTERSELECT moving from 4'b0000 to 4'b0001, the phase shift direction appears to invert between c0 and c1 with respect to the original clk. I can compensate by flipping PHASEUPDOWN, but this seems odd.

• When PHASECOUNTERSELECT is set to 4'b0010 (targeting c2), the phase does not change at all, regardless of the direction.

Environment: Quartus Prime 23.1 Standard, Stratix IV, Terasic DE4-230.

If you need additional details (project files, reports, waveforms), I’m happy to provide them. Thank you!

Best regards,

Heyang 

[FvM]

Hi,
there are several issues that cause the observed behaviour
1. unused PLL outputs are removed and respectively changing PLL counter assignment
2. PLL counter order isn't preserved without explicite setting

See below the fitter results with different settings. You need to connect all PLL counter outputs and preserve PLL counter order to get the expected counter assignment.

counter_select = 0 will e.g. manipulate 150 MHz PLL output driving Signaltap and give the appearance of reverse phase shift.

Original project settings

+--------------+------+-----+------------------+  +---------+
; Output Clock ; Mult ; Div ; Output Frequency ;  ; Counter ;
+--------------+------+-----+------------------+  +---------+
; clock1       ; 1    ; 1   ; 50.0 MHz         ;  ; C1      ;
; clock3       ; 3    ; 1   ; 150.0 MHz        ;  ; C0      ;
+--------------+------+-----+------------------+  +---------+

Fitter result with all outputs connected, counter order not preserved

+--------------+------+-----+------------------+  +---------+
; Output Clock ; Mult ; Div ; Output Frequency ;  ; Counter ;
+--------------+------+-----+------------------+  +---------+
; clock0       ; 1    ; 1   ; 50.0 MHz         ;  ; C0      ;
; clock1       ; 1    ; 1   ; 50.0 MHz         ;  ; C2      ;
; clock2       ; 1    ; 1   ; 50.0 MHz         ;  ; C3      ;
; clock3       ; 3    ; 1   ; 150.0 MHz        ;  ; C1      ;
+--------------+------+-----+------------------+  +---------+

All outputs connected, counter order preserved

set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER ON -to *

+--------------+------+-----+------------------+   +---------+
; Output Clock ; Mult ; Div ; Output Frequency ;   ; Counter ;
+--------------+------+-----+------------------+   +---------+
; clock0       ; 1    ; 1   ; 50.0 MHz         ;   ; C0      ;
; clock1       ; 1    ; 1   ; 50.0 MHz         ;   ; C1      ;
; clock2       ; 1    ; 1   ; 50.0 MHz         ;   ; C2      ;
; clock3       ; 3    ; 1   ; 150.0 MHz        ;   ; C3      ;
+--------------+------+-----+------------------+   +---------+

I compiled the design with Quartus 19.1 because I don't have 23.1 installed. Quartus 24.1 std dropped an error with counter_select signal that I didn't understand. Looks like a Quartus 24.1 bug. 

Regards
Frank

P.S.: Restoring the archive once more in 24.1 didn't reproduce a compilation error. All above reported PLL counter problems are identical to 19.1. 
 

[Heyang]

Hi Frank,

Thank you very much for your prompt answer!

I have tried connecting all three clocks (c0, c1, and c2) to the physical pins, and used c3 as the SignalTap clock. I also ran the TCL command you suggested in the TCL window—thank you for sharing that. Below is the fitter PLL summary:

clock0	1	1	50.0 MHz	0 (0 ps)	3.75 (208 ps)	50/50	C0
clock1	1	1	50.0 MHz	0 (0 ps)	3.75 (208 ps)	50/50	C1
clock2	1	1	50.0 MHz	0 (0 ps)	3.75 (208 ps)	50/50	C2
clock3	4	1	200.0 MHz	0 (0 ps)	15.00 (208 ps)	50/50	C3

As shown, the counters have been correctly assigned to the clocks.

Unfortunately, the behavior still seems unusual. I have attached a SignalTap screenshot where I added the three clocks to visualize the waveforms. As you can see, the c0 clock is phase-shifted relative to c1 and c2, even though the PLL phasecounterselect value I chose is 2 to phase shift c2 instead of c0, as indicated in the screenshot. This observation is in agreement with the oscilloscope measurements of the physical signals. 

c0 and c1 are still shifting in opposite directions, even after connecting all clock outputs to the pins and applying the TCL command.

Apologies if I have overlooked something trivial, and thank you in advance for your time and valuable assistance!

Best regards,

Heyang

[FvM · Accepted solution]

Hi,
additional problem, phasecounter_select mapping is different than expected. See Stratix IV handbook.

Regards
Frank

[Heyang]

Hi Frank,

Thank you very much for this information! I have completely missed this part. I only checked the ALTPLL User Guide but not checked this one. This helped me a lot. Thank you! Have a great day!

Best regards,

Heyang