I have a design where I have an incoming 125MHz clock that I'm feeding to a PLL. The 10M25 IP configuration for the PLL is largely automatic, but is choosing a VCO frequency of 500MHz, which is out of spec according to the datasheet, which states the VCO frequency should be between 600 and 1300MHz. I'm not getting PLL lock and have tried several things before looking closely at the PLL configuration and noticing this out-of-spec VCO frequency.
I can't seem to change this, or even try to get the IP configuration tool to let me enter a manual mode where I can choose a better VCO frequency and M/N dividers.
I have some ability to adjust the incoming clock to the PLL, but 62.5 and 31.25MHz also hold the VCO frequency to 500MHz.
Why is the tool choosing 500MHz, and how can I fix this? I'm using Quartus Prime Lite 18.1.0 Build 625 on Linux.