hii testing the ASI-Megfanction in quartus 13. I see that the data valid is not constant high for the 188 byte frame. It is per byte high. http://www.alteraforum.com/forum/attachment.php?attachmentid=9338&stc=1&d=1409645072 in the "Asynchronous Serial Interface (ASI) MegaCore Function User Guide" Altera write: --- Quote Start --- The ASI MegaCore function demonstrates how to transmit or receive packets over an ASI. The ASI MegaCore function works with 270 megabits per second (Mbps) DVBASI, as defined by the DVB-ASI specification EN 50083-9 from CENELEC / December 2002 “Cable networks for television signals, sound signals and interactive services. Part 9: Interfaces for CATV/SMATV head-ends and similar professional equipment for DVB/MPEG2 transport streams”. --- Quote End --- But i can not find this form of data vaild in the EN 50083-9. Where can i find this form and other forms of the data valid? Thanks
The question is what is the clock speed? 270MBits/s is only a 33.75MHz dword rate. Assuming your image has valid high for 1 clock and low for three, it seems that the system clock is 135MHz.ASI runs at a constant data rate, so needs the data valid to run at this data rate when the clock is faster. From your diagram, if the dvalid was high for the entire frame, you would collect multiple sync bytes (0x47), and it would cause all sorts of problems.
Ah cool. Thanks.i have connect the clock like in the user manual from altera: http://www.altera.com/literature/ug/ug_asi.pdf (page 4-5) http://www.alteraforum.com/forum/attachment.php?attachmentid=9344&stc=1&d=1409817961 the clock 337 and 337 with 90° and the clock 135 are from one PLL.