FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP


Honored Contributor II

Hi guys: 

Why do we need symbols per beat and bits per symbol to define a data width? Is the beat a clock cycle? 

And why there is no full and empty signal in single clock FIFO(Qsys)?How can I generate those? 

Thanks in advance 


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Honored Contributor II

A beat represents the transfer between the streaming source and sink, which is typically when valid and ready are both high. Symbols represent the smallest unit of transfer within a beat. The data width of the ST port is symbols/beat * bits/symbol. When deal with transferring data between memory and streaming typically I use a symbol size of 8 bits since that what Avalon-MM uses as a byte size and the appropriate number of symbols to achieve the correct width for the transfer. 


In Avalon-MM speak beats are transfers within a burst and symbols are the bytes per transfer. 


The reason why full and empty are not exposed is because they are used to drive the ready and valid signals. So if the FIFO is empty then it's source should not assert ready, and when it's full the FIFO should not assert ready.
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