About EMIF recalibration and transceiver recalibration

[lambert_yu]

Hi,

   I have one problem:

  For EMIF IP, if I select hard-controller and hard-phy style, when I provide one global_reset for the global_reset pin of memory IP, will it lead to the recalibration of PHY? Or , only I provide one recalibration through writing to related register do can request one time recalibration of PHY?

  For transceiver recalibration, why I need to post one time recalibration through writing related register but not reset pin?

  Could someone provide some information about this problem?

Brs,

Lambert

[BoonT_Intel · Accepted solution]

Hi Sir,

Yes, both IP has different reset scheme, one using reset input pin while one using the register method.

I think the reason is EMIF IP does not need/support reconfiguration. So, using the single input to reset/recalibrate the IP is sufficient.

However, for XVCR, it will need reconfiguration, as what I know, during reconfiguration, the user not only need to reset the IP but also need to write into other registers to meet the requirement, so it will need register method to do all the work like reset and reconfiguration.

By the way, this is not a problem, all of these are based on the IP usage model needs.

Hope this helps.

[lambert_yu]

Hi BoonT,

  Thanks for  your reply, that meas for EMIF ip, I only send one global_reset to the global_reset_n port of EMIF IP, EMIF will execute one time recalibration, right?

Brs,

Lambert

[BoonT_Intel]

Yes, from the user access port (AvalonMM), you will see the ready signal dessert after reset and will assert back after re-calibration which trigger by the reset signal.

[lambert_yu]

Hi boonT,

    Thanks for your help.

Brs,

Lambert

[BoonT_Intel]

You're welcome.

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