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5887 Discussions

Apparent error in Agilex DDR4 EMIF IP model - "maximumPendingReadTransactions" is "1"

SCLAY
Beginner
462 Views
Hello!
 
The Agilex DDR4 EMIF IP model for Platform Designer (qpro20.4.0.72) appears to have an error in the AvMM parameters, namely, that the “maximumPendingReadTransactions” parameter is set to “1” (see attached screen capture).  I have run the DDR4 EMIF example design simulation, and can see that the parameter should be at least 16, as I can see that the EMIF accepts at least 16 outstanding reads during that simulation.
 
The AvMM spec has this to say about this case of accepting more reads than indicated by “maximumPendingReadTransactions” :
 
If a slave interface accepts more read transfers than allowed, the interconnect pending read FIFO may overflow with unpredictable results. The slave may lose readdata or route readdata to the wrong master interface. Or, the system may lock up. The slave interface must assert waitrequest to prevent this overflow.
 
The effect of this is that in the AvMM interconnect in our design, Platform Designer is only making the “agent_rsp_fifo” 2 deep, but has enabled FIFO overflow protection.  My understanding is that the interconnect will therefore throttle the AvMM masters, including writes, after the EMIF slave accepts 2 reads (one more than is “legal” for its "maximumPendingReadTransactions”).
 
While this should “work” as far as functionality is concerned, it will not “work" for our application, as more than 2 outstanding reads are required to achieve the required read bandwidth from DDR.  Furthermore, blocking all writes with only 2 reads are outstanding will throttle performance on the write side, as well.
 
As an experiment, I changed the “maximumPendingReadTransactions” parameter in the relevant places in the .qsys and .ip files, and regenerated the RTL in Platform Designer.  In that case the “agent_rsp_fifo” was changed to 17 deep, which confirms that the incorrect value for that parameter is the problem.

 

Thanks!

 

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7 Replies
yoichiK_intel
Employee
415 Views

Hi

I created the example design from Agilex DDR4 EMIF IP GUI and see the Maximum pending read transaction parameter is set to 64 as attaching.   I am not sure where this changes comes from.

SCLAY
Beginner
410 Views

Yes, that looks great.  Same screenshot of my example design is attached - it is set to "1".  What tool version are you running?

Info: Version 20.4.0 Build 72 12/14/2020 SC Pro Edition

Thanks!

 

SCLAY
Beginner
405 Views

Update - I created an empty project, added the EMIF, and wrote the EMIF example design without doing any configuration.  The parameter is set to "64".  The parameter may be changing due to either configuration or context.  I'll need to do more investigation.

 

SCLAY
Beginner
400 Views

I've found what looks like may be the problem - edit the EMIF parameters, choose the "Diagnostics" tab, and under "Performance", set the "Efficiency Monitor Mode" to anything other than "Disabled" (e.g., "Interface to Efficiency Monitor Toolkit").  Click the "Finish" button.  The "Maximum pending read transactions" becomes set to "1".  This is the configuration that produced the results in the original post.

This would appear to greatly reduce the utility of the efficiency monitor, due the performance implications listed in the original post (unless the design only issues a single read at a time!).  Please confirm.

Thanks!

 

yoichiK_intel
Employee
391 Views

Hi

I followed same way which you mentioned, using "Interface to Efficiency Monitor Toolkit" for performance option.  I still do not get the same result at my side.  I am running  Quartus pro 20.4 build72 version.

SCLAY
Beginner
387 Views

I have no explanation.  I have included 4 screenshots with the example synthesis design:

emondsA.jpg: shows edit parameters with emon disabled

emondsB.jpg: shows the max pending with emon disabled

emonenA.jpg: shows edit parameters with emon enabled (only thing changed since emondsA.jpg)

emonenB.jpg: shows the max pending with emon enabled (only thing changed since emondsB.jpg)

This is 100% repeatable for me.  Any ideas?

Thanks!

 

 

SCLAY
Beginner
381 Views

Hi!  I've attached a project that (for me) shows the problem.  Do:

  1. gunzip < emif.tar.gz | tar -xvf
  2. cd emif
  3. qsys-edit emif.qsys -qpf=emif.qpf

The only module in the diagram is the DDR4 emif, and as configured, shows "Maximum pending read transactions" as "1".

Thanks!

 

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