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5914 Discussions

About no service for the emif read request

lambert_yu
Beginner
317 Views

Hi all,

  Now I am debugging the EMIF IP (Master and Slave EMIF design) in my own custom design, before I have test the EMIF IP through the EMIF example design so I think there is no hardware issue, but there is problem when used this IP in my own custom design:

   For some case( read and write request for EMIF ip is random, and read and write operation is sequential, and all requests generated are all timinged to the emif_usr_clk of master and is related to the avalon interface signals of master, all above requests are all stored into one async fifo, and slave will read these requests when its avalon_ready signal is high and async_fifo is not empty), but from the debug signals, I found that all read requests and write requests can be executed by the master, but for the slave EMIF, though it gots all the read requests, but for the few read requests, it didn't output related read data,  is there bus contension problem or any other things which I have not notice? Or can I change the primitives of memory controller? Or do any other problems leads to this problem? Could someone give me some advices?

 

Brs,

Lambert

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5 Replies
AdzimZM_Intel
Employee
295 Views

Hi Lambert,


Do you have any warning messages when you are compiling the design?


Do you check your data bus width of the Avalon master and EMIF IP Avalon slave?


Thanks,

Adzim


lambert_yu
Beginner
282 Views

Hi Adzim,

 

     1) I make sure that there is no warning about EMIF IP after compile.

      2) I make sure that the width is right.

     Add some information:

      for the write request,  2KB/(time*IP) (sequential), for the read request, 1KB/(time*IP)(sequential), I can not make sure that DDR will write/read the same bank, bank group.

      Just for the above case,

      If the sum of write data is (2KB*N+64B*2, 2KB*(N+1)) ,  2KB@write request, 1KB@read request, there is no above phenomenon;

      If the sum of write data is (2KB*N, 2KB * N + 64B *2) for every write request (if N = 1, I will need 2*write request to complete this write operation). And the sum of read data for every read request is 1KB, the above phenomenon will be appear after FPGA runs a short time(Read and write requests are interleaved).

        1) I try to add tWTR or tRTW, tCCD, tRRD time, there is no effect for above phenomenon;

        2) I try to add high-priority for all read requests and decremente the limite of the starvation);

        3) Now I try to disable re-ordering, I will check is there effect?

 

Brs,

Lambert

lambert_yu
Beginner
251 Views

any advice?

AdzimZM_Intel
Employee
243 Views

Hi Lambert,


Sorry for the delay.


Is there any error message regarding to this?

Or it's only you received the invalid data from read request?


Thanks,

Adzim


lambert_yu
Beginner
238 Views

Hi Adzim,

     I have resolved this problem, and I closed this question.

 

 

Brs,

Lambert

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