I'm porting a design from a Xilinx device to a Cyclone5 and am trying to find a comparable signed arithmetic IP blocks using varying width inputs and outputs.ALTERA_MULT_ADD works well for for my multipliers and I can specify the input output widths as needed, however I'm not seeing a comparable add/sub block. It looks like LPM_ADD_SUB only supports same data width inputs and outputs, i'm looking for something that could be configured with input widths of 28 and 29 and an output width of 30 bits. Is anyone aware of an Altera IP block that will support this?
--- Quote Start --- for add sub you can add carry input or output which accounts for bit growth --- Quote End --- I will probably have to do this if I can't find a comparable block, as well as increase some input widths with extra 0's in the MSB slots. Since there are many instances of this in the design I am porting I was hoping for a comparable block, but I have not had success in finding one yet, figured I'd see if I was missing anything before going with this route. --- Quote Start --- lpm_add_sub ? there is parallel_add IP. you can change width by typing you own. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_lpm_alt_mfug.pdf --- Quote End --- PARALLEL_ADD looks like it only sums multiple values together (e.g. a+b+c+d...) and does not support signed values.
--- Quote Start --- PARALLEL_ADD looks like it only sums multiple values together (e.g. a+b+c+d...) and does not support signed values. --- Quote End --- 1. it can subtract only one argument in your list it will be 'a'. by the way , subtraction sometimes is pure addition ;) 2. signed values supported. let's try.