Adding SDRAM meeses with LVDS communication

[Altera_Forum]

Hi, 

  I have a design comprising PCIe, DDR2, and multiple LVDS channels to connect a Stratix II GX FPGA to a Cyclone III FPGA. Using Signaltap I have verified that my design works well when I have just PCIe soft IP and LVDS SERDES IP in my design. But, as soon as I add DDR2 IP (extracted from Altera Reference 'PCIe-DDR2' design), my LVDS signals received at Cyclone are different from the ones I transmit at Stratix end. If I remove the DDR2 from my design, LVDS again seems to work fine. I would appreciate any help or pointers.   PS: I haven't attached the design files due to their large size and some IP issues but would be happy to present any specific information which might be helpful in debugging this problem.   Thanks

[Altera_Forum]

Signal timing may change with implementing DDR2 interface and IP. The first question is, how you achieved phase alignment in the original design for LVDS receivers at the Cyclone III. Another, what' the nature of the transmission errors?

[Altera_Forum]

Is the DDR2 on the SIIGX or Cyclone III? Can you add something to disable the DDR2 in system, so it's the same place and route you can see it work and then not work? Have you verified it it's a single lane of multiple lanes that are corrupted, or even the whole thing? 

 My guess is there's some sort of board-level issue. Ground-bounce, cross-talk, SSN, etc., but it's hard to say. Good luck.

[Altera_Forum]

FvM, 

I am using a PLL on stratix to generate two clock signals - one to drive SERDES Tx on Stratix and another to drive a PLL on Cyclone. Cyclone PLL in turn generates the clock for SERDES Rx. The error is that when I use SignalTap to view 10-bit data received at Cyclone it does not match the 10-bit data sent by the Stratix.   Rysc, DDR2 is on the SIIGX. When I leave its constraints in the project but remove the module from my design, things work fine. Did you mean that I should keep it in design but may be leave it unconnected or disable the clocks driving it? I have one lane going from Stratix to Cyclone, which is corrupted, and 4 lanes coming back from Cyclone to Stratix, which seem correct. (I am going to re-verify that since I did that test 2 days back). The stratix board is the development kit while Cyclone board is a custom one.   Thanks you guys for such prompt responses.

[Altera_Forum]

The fact, that the LVDS connection is inter-board suggests, that Rysc's assumption of signal quality issues may be correct. In this cases, you should check the LVDS waveforms and possible changes when operating the RAM. 

 Did you try to adjust the LVDS receiver phase in both cases? Is the word alignment guaranteed by the reference clock unequivocally?

[Altera_Forum]

Just one important warning before you commit further. It happened to me once. Don't depend 100% on signaltap. I used to get wrong data from signaltap in some builds and we termed it clock slip. The best check is in firmware itself, device a simple internal test to latch any error and flag it out on led.