Your advice please.I already have two successful designs on different PCBs 1) lwIP/FreeRTOS TCP/IP protocol stack running on ARM microcontroller 2) Another project successfully ported from 8051 microcontroller to NIOSII on Cyclone III I now want to port the ARM product to NIOSII on CycloneIII FPGA. The plan is to purchase a NEEK board and the Embedded IP Suite for the development process. I've scanned the NIOS forums for the various problems people have experienced. I'm please to have spotted that BillA has contributed an Altera TSE driver for lwIP (June 21 2010) :) thanks, Bill Before I commit to spending money (and loads of time) would those who have done something very similar care to share their experience/advice with me. Which of the various component choices would be least painful? I'm currently working with NIOS EDS 9.1 and QuartusII 9.1sp1. many thanks
In reply to fheinemanI did succeed in getting a TCP/IP protocol stack working on a Cyclone III board. This was in December 2010. I did try porting this work onto another similar board to produce a product but this ran into difficulties and the project was abandoned. So my memory is rather sketchy. I was able to demonstrate - a very simple web server - Modbus protocol The components were NEEK board and the Embedded IP Suite Quartus II 9.1sp1 NIOS II EDS 9.1 SBT µCOS II Altera TSE MAC Altera SGDMA Altera webserver.c Altera http.c Iniche stack v3.1 from Altera The areas that caused the most problems were: Connections between FPGA and the PHY - you have to work this out for yourself and get it right. Removing µCOS II. After getting the stack working with the OS I then converted to using Superloop to avoid the licence fee. This configuration is not documented and there is no simple# define which will remove the OS easily. I never understood completely how Chronos fitted in. I never attempted to use lwIP with NIOS, but I still use it to roll out new products based on an ARM microcontroller.
Thank you bmarshall for your informative reply. It is helpful to know that you ran into the very same issues that I have faced. I had to spend a LOT of time on the FPGA-to-PHY interface, which is especially disturbing as it is such a simple interface. As it turned out, I ended up with a very straight-forward solution. The lack of comprehensive documentation made this process far more difficult than it needed to be.I now have the iniche TCP/IP stack running on a custom board with 512K of SRAM instead of the cumbersome SDRAM. From what you wrote along with the comments and questions of so many others, I can see that I still have a daunting task ahead to bring this design to the product level. I just hope I can get there before the project is abandoned. I am always happy to share my findings with others and would really appreciate hearing from someone who has brought a similar product to market with the Nios II and Qsys. Thanks again for your comments.