I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down.
Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBUGGING IT. BECAUSE ITS WITH VERY OLDER VERSION (QUARTUS-12.1).
NOT ABLE TO GENERATE THE PROJECT FILES FROM FOLLOWING EXAMPLE.
Dont get why waitrequest goes down.
Any help will highly appreciated.
Thanks in advance
The quartus version in wiki is too old. I suggest you to re-generate the example design in newer version.
There is a known issue on DDR3 SDRAM Controller MegaCore supporting UniPHY.
Please refer to below KDB solutions on some suggestions which may improve the efficiency of the Avalon interface.
Hope this helps.
Thank you for replying.
I will try to solve it from given links.
can we regenerate the example design just to write or read the data into ddr3 controller without qsys?
because i generated the reference design and i tried to simulate it as per instruction, nothing is happening. there is README.txt file, which clearly says that you just need to run it with do run.do
But thats simulating the design and adding all the waves the design but signal shows just 0/x/z.
Let me know your thoughts.
Thank you for guidance. so, i generated the design. But its same for simulation also. I connected my module to ddr3 controller at avl interface. but waitrequest is not asserting after one burst.
Thank You in advance,