FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6545 Discussions

Agilex 100G E-Tile MAC interface tx_ready is continuously flipping after linkup.

Lance313
Beginner
711 Views

The following is similation wave. The tx_ready signal is  is continuously flipping after linkup,  whether user send packet or not. We also observe this phenomenon by testing on fpga board. 

1. Is this phenomenon normal?

2. How to eliminate flipping of tx_ready when bus is idle?

Lance313_0-1723778406658.jpeg

Quartus version: 22.2

E-tile configuration:

Lance313_1-1723778474918.jpegLance313_2-1723778481504.jpeg

 

Labels (1)
0 Kudos
4 Replies
ZiYing_Intel
Employee
626 Views

Hi,

 

You may use i_tx_error for testing, to generate errored packets. To invalidate an errored frame, end it with i_tx_endofpacket and assert i_tx_error. If the frame is good, deassert i_tx_error. For further information, you may refer to link below, Figure 40, pg 128, https://www.intel.com/content/www/us/en/docs/programmable/683468/23-2/tx-mac-interface-to-user-logic.html

 

Best regards,

zying


0 Kudos
Lance313
Beginner
618 Views

Hi, 

Thanks for your reply. But my question is about o_tx_ready.  What is the purpose of generating errored packets? 

0 Kudos
ZiYing_Intel
Employee
510 Views

Hi,


Could you share your .qar file? So that I can try replicate the issue from my side.


Best regards,

zying


0 Kudos
ZiYing_Intel
Employee
483 Views

Hi,

 

Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

 

Best regards,
zying

0 Kudos
Reply