DDR3 DDR4 ECC signals ctrl_ecc_readdataerror

[TSchu3]

Hello, I am attempting to implement the Hard memory controller with ECC enabled for an Arria 10 device.  I am looking for further information on the following signals-

ctrl_ecc_readdataerror-  This signal is described in the user guide but is not generated in the IP for either DDR3 or DDR4 when I select ECC.  How can I enable this signal?

ctrl_ecc_user_interrupt-  This signal is generated but there is very little information about it in the user guide.  Where can I find more information on this signal?  When does it assert?  Is it active High or Low?  etc.

Thank you!

[AdzimZM_Intel]

Hi TSchu3,

Please use Quartus Pro edition to enable the ctrl_ecc_readdataerror signal.

The Quartus Standard edition doesn't support this feature.

Regards,

Adzim

[AdzimZM_Intel]

Hi @TSchu3 

Is there any further question in this thread?

The ctrl_ecc_user_interrupt signal is the output conduit from EMIF IP that active when there is a bit error.

This signal should be active high.

Regards,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.