Agilex 3 (GTS AXI) PCIe IP

[GabrielC]

I previously asked probably in the wrong category, IP is a better match.

I plan a new board using PCIe 3 and LPDDR4 using Agilex3.
I already have a prototype project using an existing Cyclone 5 board, and it worked just fine.
I tried to move to Agilex3 (Quartus Prime Pro 25.1.1), but the IP is completely different.

My logic was designed with Avalon MM components, and for Cyclone 5 the IP was handling all TLP bridging to MM, and also used the tx channel for bus mastering (I used msgdma).

But I could not find anything similar for Agilex 3...

There is a PIO design example; even if it works, I also need tx bus mastering.

Do I have to handle all TLP myself?? I don't have the experience for this, might not be realistic...

Disabling the device compatibility, I see a lot for potential IP... e.g. GTS AXI Multichannel DMA, why is it just for Agilex 5?

I see online SSGDMA IP DMA PCIe... also only for Agilex 5??

Why this limitation?

Thanks,
Gabriel

[Wincent_Altera · Accepted solution]

Hi Gabriel,

I am seeing the exactly same question asked at other thread.

https://community.intel.com/t5/forums/forumtopicpage/board-id/programmable-devices/message-id/101235#M101235

I will close this and move the support to that thread to avoid duplicate information.

Regards,

Wincent_Altera