FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6020 Discussions

Agilex FPGA PCIe Gen5 Example Design Simulation Error

TBalu
Novice
525 Views

 


Unsing Quartus Prime Pro Edition 21.2. Generated PCIe Gen5 1x16 native endpoint Example design. When compiling in Modelsim Intel FPGA Starter Edition 2021.1, I get the following error:

Top level modules:
# pcie_ed_tb
# End time: 15:25:41 on Nov 08,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# [exec] elab_debug
# vsim -voptargs="+acc" -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L tennm_ver -L tennm_hssi_ver -L tennm_hssi_f0_ver -L tennm_hssi_r0_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L tennm -L tennm_hssi -L intel_rtile_pcie_tbed_100 -L dut_pcie_tb_ip -L altera_avalon_onchip_memory2_1930 -L pcie_ed_MEM0 -L altera_s10_user_rst_clkgate_1932 -L pcie_ed_resetIP -L intel_pcie_pio_1024_191 -L pcie_ed_pio0 -L intel_rtile_pcie_ast_200 -L pcie_ed_dut -L altera_merlin_master_translator_191 -L altera_merlin_slave_translator_191 -L altera_merlin_master_agent_191 -L altera_merlin_slave_agent_191 -L altera_avalon_sc_fifo_1930 -L altera_merlin_router_1920 -L altera_avalon_st_pipeline_stage_1920 -L altera_merlin_burst_adapter_1920 -L altera_merlin_demultiplexer_1921 -L altera_merlin_multiplexer_1921 -L altera_mm_interconnect_1920 -L pcie_ed -L pcie_ed_tb pcie_ed_tb.pcie_ed_tb
# Start time: 15:25:42 on Nov 08,2021
# Loading pcie_ed_tb.pcie_ed_tb
# ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_f0_ver' at "tennm_hssi_f0_ver".
# No such file or directory. (errno = ENOENT)
# ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_f0_ver' at "tennm_hssi_f0_ver".
# No such file or directory. (errno = ENOENT)
# ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver".
# No such file or directory. (errno = ENOENT)
# ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver".
# No such file or directory. (errno = ENOENT)
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) Instantiation of 'rtile_s20_v0' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /pcie_ed_tb/pcie_ed_inst/dut/dut File: ../../../../ip/pcie_ed/pcie_ed_dut/intel_rtile_pcie_ast_200/sim/pcie_ed_dut_intel_rtile_pcie_ast_200_arwqpni.sv Line: 63027
# Searched libraries:
# C:/Pci_test/intel_rtile_pcie_ast_0_example_design/pcie_ed_tb/pcie_ed_tb/sim/mentor/libraries/intel_rtile_pcie_ast_200
# C:/Pci_test/intel_rtile_pcie_ast_0_example_design/pcie_ed_tb/pcie_ed_tb/sim/mentor/libraries/work
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/altera
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/220model
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/sgate
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/altera_mf
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/altera_lnsim
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/tennm
# C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/tennm_hssi_all


Seems like 'rtile_s20_v0' file is missing.
Also ,

Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver".
Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver".

Please suggest on how to fix this error?

 

1 Reply
alexislms
New Contributor III
179 Views

Same here with Quartus Pro 22.1 and Questa SE provided with it.

Followed UG-20330.

Reply