Alt_asmi

[Altera_Forum]

Hi, 

 I have a CyCIII connectet to a serial configuration device. I´m able to configure the CYC III with active serial.  Now I want to access the Flash with the ALT_ASMI_Parallel_Interface.  I pulled the signal read_sid to HIgh... and about 40 clock cycs later the busy signal (ouptput) goes to low. The problem is that the epcs_id (8 bit output) is allways 0xFF.  What could there be wrong?  clk_in frequency of alt_asmi is 12.5Mhz from a PLL.  Thanks  Chris

[Altera_Forum]

I too have a similar issue with a cyc3 . Probing the EPCS16 shows that after FPGA configuration the EPCS nCS signal goes low. When the ASMI function is used to preform a read the nCS is driven high when the operation code is sent out. Sort of behaves as though the nCS is inadvertantly inverted in the megafunction.

[Altera_Forum]

The altera megafunction shall work with EPCS devices. I do not have an EPCS device but a ordinary serial flash from STM. 

 If you have a standard EPCS device this shall work for sure.  I only have tested it in simulation and not in hardware. Do you probing in hardware?  Ensure that you have selected the right EPCS device in the megacore wizard. In hardware you have to ensure to use the correct pins on the cylone III device.

[Altera_Forum]

Yep, I'm using the correct device n the megafunction (epcs16). It's failing in the actual hardware where as I mentioned earlier the nCS behaves as though it's being inverted. The traces below show the operation during a read through the asmi function. The signals from top to bottom are conf_done, asdi, nCS, data, dclk. 

 http://patobravo.smugmug.com/photos/218312442-L.jpg

[Altera_Forum]

if the measurement is OK, the nCS should be inverted. If you are sure that this signal comes directly from the megacore, you should ask the altera technical support with a request on the homepage. This requests are often replied fast. You can also post your solution here.  

 You can also try to invert the nCS signal by your self and check what happens than :)

[Altera_Forum]

--- Quote Start ---  You can also try to invert the nCS signal by your self and check what happens than :)  --- Quote End ---    Yea, I'm waiting to hear from MySupport. I'd try inverting but I use the same part for configuration. During configuration the sense of nCS is correct, it's after the FPGA enters user mode it gets hosed.

[Altera_Forum]

Hello John, 

 A software bug report has been filed and we are all awaiting the solution.  Your angel.

[Altera_Forum]

For closure: the megafunction did genrate code that inverted nCS in user mode and a smalll portion of megafunction code was required to be replaced. I'm told this will be fixed with Q8.

[Altera_Forum]

Hi, 

I have similar problem on Cyclone II EP2C5Q208C8N. Sometimes I can't read all EPCS configuration memory because it seams that nCS goes High from altasmi megafunction.  Anybody has found a solution ?  Ciao. Vittorio

[Altera_Forum]

The fix they gave me for Cyc III worked and they had promised me it'd be incorporated into Quartus 8; I haven't checked that yet though and probably won't until the next product update.

[Altera_Forum]

Hi Johns, 

what is the solution they gave you ?  Vittorio

[Altera_Forum]

They had me modify the file epcs_asmi.v lines as follows: 

original code:  initial  ncs_reg = 0;  // synopsys translate_on  always @ ( negedge clkin_wire or posedge end_ophdly)  if (end_ophdly == 1'b1) ncs_reg <= 1'b0;  else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b1;  modify it to:  initial  ncs_reg =1;  // synopsys translate_on  always @ ( negedge clkin_wire or posedge end_ophdly)  if (end_ophdly == 1'b1) ncs_reg <= 1'b1;  else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b0;   Of course YMMV. But I'd be really surprised if CycII had the same issue, that's a relatively mature product. But then things get broken with every new release so I guess it may not be that hard to beleive.

[Altera_Forum]

I use: 1. Quartus 8 + SP1 2. Cyclone III 3. EPCS64 4. Verilog     If using the mega wizard as is, and it have major bug, the CSn line to the EPCS64 is active hi and should be active low. I found manual correction in altera forum    http://www.alteraforum.com/forum/archive/index.php?t-1141.html (http://www.alteraforum.com/forum/archive/index.php?t-1141.html)   johns April 9th, 2008, 10:50 AM They had me modify the file epcs_asmi.v lines as follows: original code: initial ncs_reg = 0; // synopsys translate_on always @ ( negedge clkin_wire or posedge end_ophdly) if (end_ophdly == 1'b1) ncs_reg <= 1'b0; else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b1;  modify it to: initial ncs_reg =1; // synopsys translate_on always @ ( negedge clkin_wire or posedge end_ophdly) if (end_ophdly == 1'b1) ncs_reg <= 1'b1; else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b0;   Manually change the verilog file This fix the issue, but still one major issue: The pin DCLK to EPCS64 is always active; this core should turn ON the clock only after try to access to the EPCS64 and not all the time (power issue, EMI/RFI issues)   Please send me quick correction to this issue as well 

[Altera_Forum]

This issue has been fixed in QII 9.0. 

 But the manual does not document that "Device and Pin Options" -> "Dual-Purpose pins" must all be set to "Use as regular I/O" otherwise the communication to the EPCS is not established. That is omission in the manual is IMHO a bug.

[Altera_Forum]

When I look at the "Device and Pin Options" dialog under "Dual-Purpose pins" the only possibility allowed in the drop down box for the ADS0, nCS0 pins is "As input tri-stated" there is no other choice. For the pin nCEO there are two choices listed "Use as programming pin" and "Use as regular I/O". I will try to see if it works with this setting for ADS0 and nCS0. This is for an EP2C8 with an EPCS4 under Quartus II v9.0.

[Altera_Forum]

--- Quote Start ---  the only possibility allowed in the drop down box for the ADS0, nCS0 pins is "As input tri-stated"  --- Quote End ---  Yes, this seems to be a Quartus "special" with Cyclone II. The Altera SFL MegaFunction is however working correctly with exactly this setting, obviously using ASDO, NCSO and DCLK as output in user mode. So I would expect altasmi to work as well, despite of this setting.  Another option is to set PS configuration in Quartus, but actually configure AS with MSEL. Then you get free choose of dual-purpose pin configuration again. I didn't try with Cyclone II, but I needed this workaround with Cyclone III due to some oddities of previous Quartus versions.

[Altera_Forum]

I can confirm that the Cyclone II can read the EPSC4 using altasmi_parallel with ADS0 and nCS0 set to "As input tri-stated" and nCE0 set to "use as regular I/O".