Altera Cyclone V PLL in zdbfbclk configuration

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Altera Cyclone V PLL in zdbfbclk configuration

1,662 Views

Hi,

I've recently started using Altera's PLLs for a Cyclone V project. I'm creating a PLL, with the IP Wizard, with zero-delay buffer (zdbfbclk) mode enabled. I want to use the zdbfbclk port to drive the clock signal I desire. However, I have not connected the single out clock port to anything. This results in the following warning:

Warning: OUTCLK port on the PLL is not properly connected on instance pllTdm:pllTdmI|pllTdm_0002:plltdm_inst|altera_pll:altera_pll_i|general[0].gpll. The output clock port on the PLL must be connected.

What is the proper way of connecting this port? Do I really need it? Am I correct in assuming the zdbfbclk can provide the clock signal I desire?

Any pointers/references to using this mode properly would be great.

Thanks in advance.

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.