ALTFP_MULT always return 0

[Altera_Forum]

Hi everyone, I'm new to fpga/verilog and met a weird problem when using altfp_mult ip core. 

 --------------------------------- I am using de2i-150 developing board, which has an Intel Atom CPU and a Cyclone IV FPGA. I need to finish a CPU and FPGA synergistic task, using PCIE for communicating. The task itself is pretty simple: CPU sends two float numbers to FPGA, FPGA multiplies the numbers and then sends the result back.   The ALTFP_MULT ip core is like this:  fp_mul (clock，dataa，datab，result);//dataa, datab, result are of 32 bits width  -------------------------------- So the problem is: I successfully send data from CPU to dataa and datab ports (I show the data on a 7-segment display). However, the result is always 0! I also tried making dataa and datab fixed to two numbers, such as dataa === 32'b1, datab === 32'b2, and the result is correct. But when dataa and datab is connected to PCIE, then the result is always 0.  -------------------------------- I've been struggling on this problem for several days and couldn't figure it out. I really appreciate every help and every advice, thanks!

[Altera_Forum]

Your problem sounds like you are not correctly storing 'dataa' and 'datab' in registers after you write them from PCIe. 

 If you look closely (SignalTap) I think you will find that the result isn't always 0, but it is only zero when one or more of the inputs are also zero.