Hello people!I wanted to translate a simulink model (control block) into VHDL code so that I can use it in a custom project I have already made. How is this possible? I have seen at the Altera DSP builder manual that as soon as the simulink model is ready, the block will get compiled and directly downloaded in the device. How can I just compile it into VHDL code and then how do I incorporate it into my already existing project? Thank you in advance!