lpm_divide use for division with more than 64 bit

[Altera_Forum]

Hello everyone, 

 I am want to divide two 96 bit unsigned integer signals (std_logic_vector). For this I use the MagaWizard Plug-In Manager and the lpm_divide IP in quartus10.1. When compiling the following error occurs:   Error: In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64  Why is there a limit to 64 bit?   The Integer Arithmetic Megafunctions User Guide from 2013.06.10 (http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf) say's on site 5: "Supports data width of 1 – 256 bits".  Is the above statement only related to newer version like quartus13.1 and a upgrade solves my problem? If yes, wich is the lowest possible quartus version number to use lpm_divide for more than 64 bit?   

[Altera_Forum]

LPM Divide only supports widths of 1-64 bits. 

Why do you need such a huge divider?

[Altera_Forum]

What is than the meaning of: -> The Integer Arithmetic Megafunctions User Guide from 2013.06.10 (http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf) say's on site 5: "Supports data width of 1 – 256 bits".

[Altera_Forum]

Do you need a pipelined design? Can you suffer some wait cycles? You could do a bit by bit difference method if you have some spare clock cycles. See the Advanced Synthesis Cookbook for an example (http://www.altera.com/literature/manual/cookbook.zip)

[Altera_Forum]

I can only assume it's a missprint, as the LPM_WIDTH parameter only goes up to 64

[Altera_Forum]

--- Quote Start ---  Why do you need such a huge divider?  --- Quote End ---    I'm implementing a precision time protocol PTP slave. For this I have to make a real time clock with adjustable speed. To realize this i increas the real time clock with a timestep at each clock cycle.  Furthermore i measure elapsed time intervals at the PTP Master and the PTP slave. If the slave and master intervals are not equal i have to adjust the timestep. Such interval consist of 80 bit nanoseconds and 16 bit subnanoseconds (nanoseconds*2^16) = 96 bit. To adjust the timestep i want to calculate how many clock cycles of the slave created the current error beetween slave and master  and with this the offset which have to add to the old timestep to correct this error.    --- Quote Start ---  Do you need a pipelined design? Can you suffer some wait cycles? You could do a bit by bit difference method if you have some spare clock cycles. See the Advanced Synthesis Cookbook for an example (http://www.altera.com/literature/manual/cookbook.zip)  --- Quote End ---    I need no pipelined design. I can wait some cycles but this will rise the overall error. I will have a look in the Cookbook.

[Altera_Forum]

If my calculator isn't broken, 2^80 nanoseconds is about 38 million years. Are you sure you need so big numbers? Especially if you are working with relative time intervals, you can safely assume that your values will be much lower than 96 bits, and use a smaller divider.

[Altera_Forum]

--- Quote Start ---  If my calculator isn't broken, 2^80 nanoseconds is about 38 million years. Are you sure you need so big numbers? Especially if you are working with relative time intervals, you can safely assume that your values will be much lower than 96 bits, and use a smaller divider.  --- Quote End ---    Yes I can use numbers smaller than 64 bit.

[Altera_Forum]

there is a serial divider in the Advanced Synthesis Cookbook that may be parameterizable to wider than 64 bits: 

 http://www.altera.com/literature/manual/stx_cookbook.pdf