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Altera_Forum
Honored Contributor I
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Altera FFT IP RTL simulation

Hi all! 

 

I'm stuck with Altera FFT IP core simulation in modelsim and I'm seeking your help. So some introduction: 

  • I do believe I have full license for this IP - I'm using Quartus prime standard edition 17.0;  

  • ModelSim(SE-64 10.2c) should be capable of simulation;  

  • Target is Cyclone V SE  

 

 

Steps I've taken before got here: 

  • Generate streaming 1024 point FFT core and simulation VHDL model;  

  • Add .SIP and .QIP files into project  

 

 

Now when running RTL simulation I'm getting this output: 

 

# // ModelSim SE-64 10.2c Jul 18 2013 Linux 4.14.15-1-ARCH # // # // Copyright 1991-2013 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // # do UniDAS_run_msim_rtl_vhdl.do # if ! { # file mkdir UniDAS_iputf_libs # } # # vmap altera /home/confucij/HDD/Installed/Modelsim_compiled_libraries/vhdl_libs/altera # Copying /home/confucij/HDD/Installed/modelsim_10_2c/modeltech/linux_x86_64/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Warning: Copied /home/confucij/HDD/Installed/modelsim_10_2c/modeltech/linux_x86_64/../modelsim.ini to modelsim.ini. # Updated modelsim.ini. # vmap lpm /home/confucij/HDD/Installed/Modelsim_compiled_libraries/vhdl_libs/lpm # Modifying modelsim.ini # vmap sgate /home/confucij/HDD/Installed/Modelsim_compiled_libraries/vhdl_libs/sgate # Modifying modelsim.ini # vmap altera_mf /home/confucij/HDD/Installed/Modelsim_compiled_libraries/vhdl_libs/altera_mf # Modifying modelsim.ini # vmap altera_lnsim /home/confucij/HDD/Installed/Modelsim_compiled_libraries/vhdl_libs/altera_lnsim # Modifying modelsim.ini # vmap cyclonev /home/confucij/HDD/Installed/Modelsim_compiled_libraries/vhdl_libs/cyclonev # Modifying modelsim.ini # vmap cyclonev_ver /home/confucij/HDD/Installed/Modelsim_compiled_libraries/verilog_libs/cyclonev_ver # Modifying modelsim.ini # vmap cyclonev_hssi_ver /home/confucij/HDD/Installed/Modelsim_compiled_libraries/verilog_libs/cyclonev_hssi_ver # Modifying modelsim.ini # vmap cyclonev_pcie_hip_ver /home/confucij/HDD/Installed/Modelsim_compiled_libraries/verilog_libs/cyclonev_pcie_hip_ver # Modifying modelsim.ini # if {} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Modifying modelsim.ini # # ##### Libraries for IPUTF cores # vlib UniDAS_iputf_libs/fft_ii_0 # vmap fft_ii_0 /home/confucij/HDD/Installed/Modelsim_compiled_libraries/UniDAS_iputf_libs/fft_ii_0 # ** Error: Modifying modelsim.ini # ** Error: (vmap-20) Cannot access file "/home/confucij/HDD/Installed/Modelsim_compiled_libraries/UniDAS_iputf_libs/fft_ii_0". # No such file or directory. (errno = ENOENT) # Error in macro ./UniDAS_run_msim_rtl_vhdl.do line 23  

 

If I remove .SIP file from project files, ModelSim tells me that FFT instance is not bound and all its pins have no driver. 

 

I'm relatively new to FPGA stuff and have no experience with IP cores. Can somebody give me a hint with this stuff?
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