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Altera_Forum
Honored Contributor I
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use triple speed Ethernet to connect with 88e1111, can not get rx clock from phy

i use tse core to connect with phy 88e1111,now i can receive data from the pc, but when i can not trigger tx_ctl signal at hign state, of course i can not capture frame by pc that send by FPGA. 

my configuration as follows: 

address configuration 

8'h01 32'hAAAA_AAAA 

8'h02 32'h0000_003b 

quartus version 13.0, FPGA 5AGXFB7K4F40I3 

any advice is appreciated.
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