FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5947 Discussions

use triple speed Ethernet to connect with 88e1111, can not get rx clock from phy

Altera_Forum
Honored Contributor II
802 Views

i use tse core to connect with phy 88e1111,now i can receive data from the pc, but when i can not trigger tx_ctl signal at hign state, of course i can not capture frame by pc that send by FPGA. 

my configuration as follows: 

address configuration 

8'h01 32'hAAAA_AAAA 

8'h02 32'h0000_003b 

quartus version 13.0, FPGA 5AGXFB7K4F40I3 

any advice is appreciated.
0 Kudos
0 Replies
Reply