FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6667 Discussions

Altera HP Controller bursts

Altera_Forum
Honored Contributor II
1,105 Views

Hi All,  

just a quick question regarding the Altera HP Memory Controller with DDR2: 

 

Can the HP manage to generate consecutive READs or WRITES as per Micron datasheets? (i.e. as the Micron datasheet says "data from any read burst may be concatenated with data from a subsequent read command to provide a continuous flow of data. the first data element from the new burst follows the last element of a completed burst. the new read command should be issued x cycles after the first read command, where x equals bl / 2 cycles.") 

 

Thanks.
0 Kudos
0 Replies
Reply