Honored Contributor II
12-01-2015 01:42 PM
Hi!I develop an Altera JESD204B IP core based system. I use reference design https://documentation.altera.com/#/00024250-AA$NT00073969 Cyclone V GT development board and DEV-ADC34jXX http://dallaslogic.com/prod_dev-adc34j/ I configure clocks and adc via SPI with the same parameters as JESD core. LMF 442 N 12 NP 12 K 20 Fsampling 50 MHz Device clock 100 MHz Sysref 2.5 MHz Link clk 25 Mhz Frame clk 50 MHz Basing on the reference design I perform the sequence of operations: 1. Init clk ic (See the Device clk and sysref) 2. Reset via reset_sequencer as it done in Arria based reference design, got core_pll_locked and xcvr_ready 3. Assert xcvr | link | frame resets 4. Configure adc 5. de-assert resets and clear error status regs System does not switch to ILA state and remains in CGS If I set in the 4th step (csr_sysref_singledet | csr_sysref_alwayson) I get SYSREF_LMFC_error. What steps do I need to perform to get it working? Thanks in advance!!!