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Altera_Forum
Honored Contributor I
772 Views

JESD data rate Qsys / Link Clock

Hi there, 

 

I've got 2 questions related to how to setup my JESD Qsys IP for the TI ADS54J60 ADC. 

 

  • Is it correct to fill-in a data rate of 5 Gbps in the Qsys window with the configuration as shown below? 

  • (1 Gsps * 2 ADCs * 16 bits * (10/8))/ 8 lanes 

  • Is it correct to calculate the link clock as: 5 Gbps/40 = 125 MHz? 

  • I don't really understand where this 40 is coming from/based on. 

 

 

Thank you for your help. 

 

With kind regards, 

Patrick 

 

 

 

 

Sample frequentie 

Gsps 

Samples per second 

 

 

Data rate 

Gbps 

Raw data rate per link 

 

 

Number of lanes per converter device 

 

 

Number of converters per device 

 

 

Number of octets per frame 

 

 

Samples per converter per frame 

 

 

16 

Number of conversion bits per converter 

 

 

N' 

16 

Number of transmitted bits per sample 

 

 

32 

Number of frames per multiframe 

 

 

CS 

Number of control bits per conversion sample 

 

 

CF 

Number of control words per frame clock period per link 

 

 

HD 

High density user data format 

 

 

LMFC 

16 

Link clock counts 

Local multiframe clock 

 

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Altera_Forum
Honored Contributor I
37 Views

Hi! 

 

I faced the similar problem)  

 

1. If we consider Altera IP Core the data rate is supposed to be the data rate per EACH lane (NOT total data rate per all link lanes). 

2. Link clock == Data rate (per each lane)/40 

 

User Guide, p 4-19 

"The timing reference for the JESD204B IP core.The 

link clock runs at data rate/40 because the IP core is 

operating in a 32-bit data bus architecture after 8B/ 

10B encoding." 

 

As far as I understood link clock == 125MHz, frame clock == 250MHz  

 

Best regards!
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