I have a system, wherein user logic is interfaced to DDR1 SDRAM Controller using native interface in Cyclone 2 device. The project was built in Quartus 11.1 and when we generate the DDR1 IP, either Avalon-MM or Native interface could be generated.Now, the whole idea is to change the memory module from DDR1 to DDR3 in Cyclone V device. But, when I try to generate the core, native interface is not supported and only Avalon interface is supported. Now I need some sort of code/IP which converts Avalon-MM to Native interface signals? Can anybody help me regarding this?
You have two choices: 1) Change your user logic to interface using Avalon and add Altera DDR3 controller to the project (this is your Avalon to Native DDR3 interface) or 2) Change your user logic to interface to DDR3 instead of DDR1. Which is the better choice would depend on what your user logic looks like.It's less likely that you would be able to write something that looks like native DDR1 on one end and native DDR3 on the other. I don't think there's anything like that available.
Hi Galfonz.Thanks for the reply. I am looking for a wrapper which converts DDR3 Avalon-MM interface to Native Interface, so that I need not change my user logic. Please suggest me
The cyclone V has built in DDR3 memory controller(s). If that's what you are talking about, using them is documented in the Cyclone V and Quartus handbooks. There is also the memory interface toolkit (which I've not used). You need to remove your Cyclone 2 memory controller and add the Cyclone V.